add save-state contract specification and system spec integration
This commit is contained in:
+103
-55
@@ -17,7 +17,6 @@ const Cpu = _cpu.m6502.Cpu(
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.cycle,
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);
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const Nes = @This();
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pub const spec = contract.SystemSpec{
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.name = "Nintendo Entertainment System",
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@@ -68,6 +67,10 @@ pub const spec = contract.SystemSpec{
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.writable = true,
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},
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},
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.save_state = .{
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.max_size = 32 * 1024,
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},
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};
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bus: Bus = undefined,
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@@ -127,7 +130,6 @@ comptime {
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contract.validateSystem(Nes);
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}
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pub fn videoFrame(
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self: *const Nes,
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output: usize,
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@@ -238,7 +240,7 @@ fn serviceOamDma(
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pub fn saveState(
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self: *const Nes,
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buffer: []u8,
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) error{BufferTooSmall}!usize {
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) contract.state.Error!usize {
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var offset: usize = 0;
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if (buffer.len < 8) return error.BufferTooSmall;
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@@ -247,42 +249,65 @@ pub fn saveState(
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// CPU
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if (offset + 15 > buffer.len) return error.BufferTooSmall;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.cpu.registers.pc, .little); offset += 2;
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buffer[offset] = self.cpu.registers.a; offset += 1;
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buffer[offset] = self.cpu.registers.x; offset += 1;
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buffer[offset] = self.cpu.registers.y; offset += 1;
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buffer[offset] = self.cpu.registers.sp; offset += 1;
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buffer[offset] = @bitCast(self.cpu.registers.status); offset += 1;
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std.mem.writeInt(u64, buffer[offset..][0..8], self.cpu.cycles, .little); offset += 8;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.cpu.registers.pc, .little);
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offset += 2;
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buffer[offset] = self.cpu.registers.a;
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offset += 1;
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buffer[offset] = self.cpu.registers.x;
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offset += 1;
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buffer[offset] = self.cpu.registers.y;
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offset += 1;
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buffer[offset] = self.cpu.registers.sp;
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offset += 1;
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buffer[offset] = @bitCast(self.cpu.registers.status);
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offset += 1;
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std.mem.writeInt(u64, buffer[offset..][0..8], self.cpu.cycles, .little);
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offset += 8;
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// Bus RAM & PRG RAM
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if (offset + self.bus.ram.len + self.bus.cartridge.prg_ram.len > buffer.len) return error.BufferTooSmall;
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@memcpy(buffer[offset..][0..self.bus.ram.len], &self.bus.ram); offset += self.bus.ram.len;
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@memcpy(buffer[offset..][0..self.bus.cartridge.prg_ram.len], &self.bus.cartridge.prg_ram); offset += self.bus.cartridge.prg_ram.len;
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@memcpy(buffer[offset..][0..self.bus.ram.len], &self.bus.ram);
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offset += self.bus.ram.len;
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@memcpy(buffer[offset..][0..self.bus.cartridge.prg_ram.len], &self.bus.cartridge.prg_ram);
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offset += self.bus.cartridge.prg_ram.len;
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if (self.bus.cartridge.chr_is_ram) {
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if (offset + self.bus.cartridge.chr_ram.len > buffer.len) return error.BufferTooSmall;
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@memcpy(buffer[offset..][0..self.bus.cartridge.chr_ram.len], &self.bus.cartridge.chr_ram); offset += self.bus.cartridge.chr_ram.len;
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@memcpy(buffer[offset..][0..self.bus.cartridge.chr_ram.len], &self.bus.cartridge.chr_ram);
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offset += self.bus.cartridge.chr_ram.len;
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}
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// PPU State
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const ppu_size = 1 + 1 + 1 + 1 + 2 + 2 + 1 + 1 + 2 + 2 + 4096 + 32 + 256;
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if (offset + ppu_size > buffer.len) return error.BufferTooSmall;
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buffer[offset] = self.bus.ppu.ctrl; offset += 1;
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buffer[offset] = self.bus.ppu.mask; offset += 1;
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buffer[offset] = self.bus.ppu.status; offset += 1;
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buffer[offset] = self.bus.ppu.oam_addr; offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.vram_addr, .little); offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.temp_addr, .little); offset += 2;
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buffer[offset] = self.bus.ppu.fine_x; offset += 1;
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buffer[offset] = if (self.bus.ppu.write_latch) 1 else 0; offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.dot, .little); offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.scanline, .little); offset += 2;
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buffer[offset] = self.bus.ppu.ctrl;
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offset += 1;
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buffer[offset] = self.bus.ppu.mask;
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offset += 1;
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buffer[offset] = self.bus.ppu.status;
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offset += 1;
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buffer[offset] = self.bus.ppu.oam_addr;
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offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.vram_addr, .little);
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offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.temp_addr, .little);
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offset += 2;
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buffer[offset] = self.bus.ppu.fine_x;
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offset += 1;
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buffer[offset] = if (self.bus.ppu.write_latch) 1 else 0;
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offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.dot, .little);
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offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.scanline, .little);
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offset += 2;
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@memcpy(buffer[offset..][0..4096], &self.bus.ppu.nametable); offset += 4096;
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@memcpy(buffer[offset..][0..32], &self.bus.ppu.palette); offset += 32;
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@memcpy(buffer[offset..][0..256], &self.bus.ppu.oam); offset += 256;
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@memcpy(buffer[offset..][0..4096], &self.bus.ppu.nametable);
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offset += 4096;
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@memcpy(buffer[offset..][0..32], &self.bus.ppu.palette);
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offset += 32;
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@memcpy(buffer[offset..][0..256], &self.bus.ppu.oam);
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offset += 256;
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return offset;
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}
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@@ -290,51 +315,74 @@ pub fn saveState(
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pub fn loadState(
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self: *Nes,
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buffer: []const u8,
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) error{ InvalidState, BufferTooShort }!void {
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) contract.state.Error!void {
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var offset: usize = 0;
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if (buffer.len < 8) return error.BufferTooShort;
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if (buffer.len < 8) return error.InvalidState;
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if (!std.mem.eql(u8, buffer[0..8], "6SOZNES1")) return error.InvalidState;
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offset += 8;
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// CPU
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if (offset + 15 > buffer.len) return error.BufferTooShort;
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self.cpu.registers.pc = std.mem.readInt(u16, buffer[offset..][0..2], .little); offset += 2;
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self.cpu.registers.a = buffer[offset]; offset += 1;
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self.cpu.registers.x = buffer[offset]; offset += 1;
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self.cpu.registers.y = buffer[offset]; offset += 1;
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self.cpu.registers.sp = buffer[offset]; offset += 1;
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self.cpu.registers.status = @bitCast(buffer[offset]); offset += 1;
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self.cpu.cycles = std.mem.readInt(u64, buffer[offset..][0..8], .little); offset += 8;
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if (offset + 15 > buffer.len) return error.InvalidState;
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self.cpu.registers.pc = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.cpu.registers.a = buffer[offset];
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offset += 1;
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self.cpu.registers.x = buffer[offset];
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offset += 1;
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self.cpu.registers.y = buffer[offset];
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offset += 1;
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self.cpu.registers.sp = buffer[offset];
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offset += 1;
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self.cpu.registers.status = @bitCast(buffer[offset]);
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offset += 1;
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self.cpu.cycles = std.mem.readInt(u64, buffer[offset..][0..8], .little);
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offset += 8;
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// Bus RAM & PRG RAM
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if (offset + self.bus.ram.len + self.bus.cartridge.prg_ram.len > buffer.len) return error.BufferTooShort;
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@memcpy(&self.bus.ram, buffer[offset..][0..self.bus.ram.len]); offset += self.bus.ram.len;
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@memcpy(&self.bus.cartridge.prg_ram, buffer[offset..][0..self.bus.cartridge.prg_ram.len]); offset += self.bus.cartridge.prg_ram.len;
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if (offset + self.bus.ram.len + self.bus.cartridge.prg_ram.len > buffer.len) return error.InvalidState;
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@memcpy(&self.bus.ram, buffer[offset..][0..self.bus.ram.len]);
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offset += self.bus.ram.len;
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@memcpy(&self.bus.cartridge.prg_ram, buffer[offset..][0..self.bus.cartridge.prg_ram.len]);
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offset += self.bus.cartridge.prg_ram.len;
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if (self.bus.cartridge.chr_is_ram) {
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if (offset + self.bus.cartridge.chr_ram.len > buffer.len) return error.BufferTooShort;
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@memcpy(&self.bus.cartridge.chr_ram, buffer[offset..][0..self.bus.cartridge.chr_ram.len]); offset += self.bus.cartridge.chr_ram.len;
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if (offset + self.bus.cartridge.chr_ram.len > buffer.len) return error.InvalidState;
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@memcpy(&self.bus.cartridge.chr_ram, buffer[offset..][0..self.bus.cartridge.chr_ram.len]);
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offset += self.bus.cartridge.chr_ram.len;
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}
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// PPU State
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const ppu_size = 1 + 1 + 1 + 1 + 2 + 2 + 1 + 1 + 2 + 2 + 4096 + 32 + 256;
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if (offset + ppu_size > buffer.len) return error.BufferTooShort;
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if (offset + ppu_size > buffer.len) return error.InvalidState;
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self.bus.ppu.ctrl = buffer[offset]; offset += 1;
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self.bus.ppu.mask = buffer[offset]; offset += 1;
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self.bus.ppu.status = buffer[offset]; offset += 1;
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self.bus.ppu.oam_addr = buffer[offset]; offset += 1;
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self.bus.ppu.vram_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little); offset += 2;
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self.bus.ppu.temp_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little); offset += 2;
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self.bus.ppu.fine_x = @truncate(buffer[offset]); offset += 1;
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self.bus.ppu.write_latch = buffer[offset] != 0; offset += 1;
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self.bus.ppu.dot = std.mem.readInt(u16, buffer[offset..][0..2], .little); offset += 2;
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self.bus.ppu.scanline = std.mem.readInt(u16, buffer[offset..][0..2], .little); offset += 2;
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self.bus.ppu.ctrl = buffer[offset];
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offset += 1;
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self.bus.ppu.mask = buffer[offset];
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offset += 1;
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self.bus.ppu.status = buffer[offset];
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offset += 1;
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self.bus.ppu.oam_addr = buffer[offset];
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offset += 1;
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self.bus.ppu.vram_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.temp_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.fine_x = @truncate(buffer[offset]);
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offset += 1;
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self.bus.ppu.write_latch = buffer[offset] != 0;
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offset += 1;
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self.bus.ppu.dot = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.scanline = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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@memcpy(&self.bus.ppu.nametable, buffer[offset..][0..4096]); offset += 4096;
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@memcpy(&self.bus.ppu.palette, buffer[offset..][0..32]); offset += 32;
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@memcpy(&self.bus.ppu.oam, buffer[offset..][0..256]); offset += 256;
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@memcpy(&self.bus.ppu.nametable, buffer[offset..][0..4096]);
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offset += 4096;
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@memcpy(&self.bus.ppu.palette, buffer[offset..][0..32]);
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offset += 32;
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@memcpy(&self.bus.ppu.oam, buffer[offset..][0..256]);
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offset += 256;
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}
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test "NES System - Save State Serialization Roundtrip" {
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