422 lines
11 KiB
Zig
422 lines
11 KiB
Zig
const std = @import("std");
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const contract = @import("contract");
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const _cpu = @import("cpu");
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const Bus = @import("bus.zig");
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const Cartridge = @import("cartridge.zig");
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const controller = @import("controller.zig");
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pub const Button = controller.Button;
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// Adjust this enum spelling to whatever your CPU package
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// currently exports for the Ricoh 2A03.
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const Cpu = _cpu.m6502.Cpu(
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Bus,
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.ricoh2a03,
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.cycle,
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);
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const Nes = @This();
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pub const spec = contract.SystemSpec{
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.name = "Nintendo Entertainment System",
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.video_outputs = &.{
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.{
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.max_width = 256,
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.max_height = 240,
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.format = .rgb565,
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.aspect_ratio = .{
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.numerator = 4,
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.denominator = 3,
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},
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.refresh_rate = .{
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.numerator = 60,
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.denominator = 1,
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},
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},
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},
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.audio_outputs = &.{
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.{
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.sample_rate = 44_100,
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.channels = 1,
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.format = .i16,
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},
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},
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.input_devices = &.{
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.{
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.button_count = 8,
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},
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.{
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.button_count = 8,
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},
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},
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.storage_devices = &.{
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.{
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.name = "Battery PRG RAM",
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.min_size = 0,
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.max_size = 8192,
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.persistent = true,
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.removable = false,
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.writable = true,
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},
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},
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.save_state = .{
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.max_size = 32 * 1024,
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},
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};
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bus: Bus = undefined,
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cpu: Cpu = undefined,
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/// Initialize in place.
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///
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/// `rom` must remain valid for the lifetime of this NES
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/// because Cartridge stores slices into it.
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pub fn init(
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self: *Nes,
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rom: []const u8,
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) Cartridge.Error!void {
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self.bus =
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try Bus.init(rom);
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self.cpu =
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Cpu.init(&self.bus);
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self.reset();
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}
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pub fn reset(
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self: *Nes,
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) void {
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self.bus.reset();
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self.cpu.reset();
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}
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pub fn step(
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self: *Nes,
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) ?u8 {
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const cycles = self.cpu.step() orelse return null;
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self.serviceOamDma();
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return cycles;
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}
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pub fn runFrame(
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self: *Nes,
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) void {
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self.bus.ppu.frame_ready = false;
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self.bus.apu.sample_count = 0;
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while (!self.bus.ppu.frame_ready) {
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_ = self.step() orelse
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return;
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}
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}
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pub const conformance = @import("conformance.zig");
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test {
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_ = conformance;
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}
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comptime {
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contract.validateSystem(Nes);
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}
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pub fn videoFrame(
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self: *const Nes,
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output: usize,
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) contract.VideoFrame {
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std.debug.assert(output == 0);
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return .{
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.data = std.mem.sliceAsBytes(
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self.bus.ppu.framebuffer[0..],
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),
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.width = 256,
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.height = 240,
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.pitch = 256 * @sizeOf(u16),
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.format = .rgb565,
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.frame_number = self.bus.ppu.frame_number,
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};
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}
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pub fn audioBuffer(
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self: *const Nes,
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output: usize,
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) contract.AudioBuffer {
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std.debug.assert(output == 0);
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const samples = self.bus.apu.sample_buffer[0..self.bus.apu.sample_count];
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return .{
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.data = std.mem.sliceAsBytes(samples),
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.frames = self.bus.apu.sample_count,
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.sample_rate = 44_100,
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.channels = 1,
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.format = .i16,
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};
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}
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pub fn setInput(
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self: *Nes,
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device: usize,
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input: contract.DeviceInput,
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) void {
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std.debug.assert(device < 2);
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self.bus.controllers[device]
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.setButtons(
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@truncate(input.buttons),
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);
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}
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pub fn storageView(
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self: *const Nes,
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slot: usize,
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) contract.StorageView {
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std.debug.assert(slot == 0);
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return .{
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.data = &self.bus.cartridge.prg_ram,
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.generation = 1,
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};
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}
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pub fn loadStorage(
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self: *Nes,
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slot: usize,
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data: []const u8,
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) contract.StorageLoadError!void {
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if (slot != 0) return error.InvalidSlot;
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if (data.len > self.bus.cartridge.prg_ram.len) return error.InvalidSize;
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@memcpy(self.bus.cartridge.prg_ram[0..data.len], data);
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}
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fn serviceOamDma(
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self: *Nes,
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) void {
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const page =
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self.bus.takeOamDmaPage() orelse return;
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const odd_cycle =
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(self.cpu.cycles & 1) != 0;
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// Mandatory DMA halt cycle.
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self.cpu.tick();
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// Alignment cycle when necessary.
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if (odd_cycle)
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self.cpu.tick();
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const base =
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@as(u16, page) << 8;
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for (0..256) |i| {
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// DMA read cycle.
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const value =
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self.cpu.readCycle(
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base |
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@as(u16, @intCast(i)),
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);
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// DMA write cycle.
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self.bus.ppu.writeOamDma(value);
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self.cpu.tick();
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}
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}
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pub fn saveState(
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self: *const Nes,
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buffer: []u8,
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) contract.state.Error!usize {
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var offset: usize = 0;
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if (buffer.len < 8) return error.BufferTooSmall;
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@memcpy(buffer[offset..][0..8], "6SOZNES1");
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offset += 8;
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// CPU
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if (offset + 15 > buffer.len) return error.BufferTooSmall;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.cpu.registers.pc, .little);
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offset += 2;
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buffer[offset] = self.cpu.registers.a;
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offset += 1;
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buffer[offset] = self.cpu.registers.x;
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offset += 1;
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buffer[offset] = self.cpu.registers.y;
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offset += 1;
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buffer[offset] = self.cpu.registers.sp;
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offset += 1;
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buffer[offset] = @bitCast(self.cpu.registers.status);
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offset += 1;
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std.mem.writeInt(u64, buffer[offset..][0..8], self.cpu.cycles, .little);
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offset += 8;
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// Bus RAM & PRG RAM
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if (offset + self.bus.ram.len + self.bus.cartridge.prg_ram.len > buffer.len) return error.BufferTooSmall;
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@memcpy(buffer[offset..][0..self.bus.ram.len], &self.bus.ram);
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offset += self.bus.ram.len;
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@memcpy(buffer[offset..][0..self.bus.cartridge.prg_ram.len], &self.bus.cartridge.prg_ram);
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offset += self.bus.cartridge.prg_ram.len;
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if (self.bus.cartridge.chr_is_ram) {
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if (offset + self.bus.cartridge.chr_ram.len > buffer.len) return error.BufferTooSmall;
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@memcpy(buffer[offset..][0..self.bus.cartridge.chr_ram.len], &self.bus.cartridge.chr_ram);
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offset += self.bus.cartridge.chr_ram.len;
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}
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// PPU State
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const ppu_size = 1 + 1 + 1 + 1 + 2 + 2 + 1 + 1 + 2 + 2 + 4096 + 32 + 256;
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if (offset + ppu_size > buffer.len) return error.BufferTooSmall;
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buffer[offset] = self.bus.ppu.ctrl;
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offset += 1;
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buffer[offset] = self.bus.ppu.mask;
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offset += 1;
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buffer[offset] = self.bus.ppu.status;
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offset += 1;
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buffer[offset] = self.bus.ppu.oam_addr;
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offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.vram_addr, .little);
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offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.temp_addr, .little);
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offset += 2;
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buffer[offset] = self.bus.ppu.fine_x;
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offset += 1;
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buffer[offset] = if (self.bus.ppu.write_latch) 1 else 0;
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offset += 1;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.dot, .little);
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offset += 2;
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std.mem.writeInt(u16, buffer[offset..][0..2], self.bus.ppu.scanline, .little);
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offset += 2;
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@memcpy(buffer[offset..][0..4096], &self.bus.ppu.nametable);
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offset += 4096;
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@memcpy(buffer[offset..][0..32], &self.bus.ppu.palette);
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offset += 32;
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@memcpy(buffer[offset..][0..256], &self.bus.ppu.oam);
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offset += 256;
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return offset;
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}
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pub fn loadState(
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self: *Nes,
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buffer: []const u8,
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) contract.state.Error!void {
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var offset: usize = 0;
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if (buffer.len < 8) return error.InvalidState;
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if (!std.mem.eql(u8, buffer[0..8], "6SOZNES1")) return error.InvalidState;
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offset += 8;
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// CPU
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if (offset + 15 > buffer.len) return error.InvalidState;
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self.cpu.registers.pc = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.cpu.registers.a = buffer[offset];
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offset += 1;
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self.cpu.registers.x = buffer[offset];
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offset += 1;
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self.cpu.registers.y = buffer[offset];
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offset += 1;
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self.cpu.registers.sp = buffer[offset];
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offset += 1;
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self.cpu.registers.status = @bitCast(buffer[offset]);
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offset += 1;
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self.cpu.cycles = std.mem.readInt(u64, buffer[offset..][0..8], .little);
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offset += 8;
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// Bus RAM & PRG RAM
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if (offset + self.bus.ram.len + self.bus.cartridge.prg_ram.len > buffer.len) return error.InvalidState;
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@memcpy(&self.bus.ram, buffer[offset..][0..self.bus.ram.len]);
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offset += self.bus.ram.len;
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@memcpy(&self.bus.cartridge.prg_ram, buffer[offset..][0..self.bus.cartridge.prg_ram.len]);
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offset += self.bus.cartridge.prg_ram.len;
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if (self.bus.cartridge.chr_is_ram) {
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if (offset + self.bus.cartridge.chr_ram.len > buffer.len) return error.InvalidState;
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@memcpy(&self.bus.cartridge.chr_ram, buffer[offset..][0..self.bus.cartridge.chr_ram.len]);
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offset += self.bus.cartridge.chr_ram.len;
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}
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// PPU State
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const ppu_size = 1 + 1 + 1 + 1 + 2 + 2 + 1 + 1 + 2 + 2 + 4096 + 32 + 256;
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if (offset + ppu_size > buffer.len) return error.InvalidState;
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self.bus.ppu.ctrl = buffer[offset];
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offset += 1;
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self.bus.ppu.mask = buffer[offset];
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offset += 1;
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self.bus.ppu.status = buffer[offset];
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offset += 1;
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self.bus.ppu.oam_addr = buffer[offset];
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offset += 1;
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self.bus.ppu.vram_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.temp_addr = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.fine_x = @truncate(buffer[offset]);
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offset += 1;
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self.bus.ppu.write_latch = buffer[offset] != 0;
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offset += 1;
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self.bus.ppu.dot = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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self.bus.ppu.scanline = std.mem.readInt(u16, buffer[offset..][0..2], .little);
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offset += 2;
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@memcpy(&self.bus.ppu.nametable, buffer[offset..][0..4096]);
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offset += 4096;
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@memcpy(&self.bus.ppu.palette, buffer[offset..][0..32]);
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offset += 32;
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@memcpy(&self.bus.ppu.oam, buffer[offset..][0..256]);
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offset += 256;
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}
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test "NES System - Save State Serialization Roundtrip" {
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// Construct dummy iNES NROM header + 16K PRG + 8K CHR
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var rom: [16 + 0x4000 + 0x2000]u8 = [_]u8{0} ** (16 + 0x4000 + 0x2000);
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@memcpy(rom[0..4], "NES\x1a");
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rom[4] = 1; // 16K PRG
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rom[5] = 1; // 8K CHR
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var nes: Nes = undefined;
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try nes.init(&rom);
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// Mutate state
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nes.cpu.registers.pc = 0x1234;
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nes.cpu.registers.a = 0x42;
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nes.bus.ram[0x05] = 0xAA;
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nes.bus.ppu.vram_addr = 0x2050;
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var save_buf: [32768]u8 = undefined;
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const bytes_written = try nes.saveState(&save_buf);
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// Reset nes
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nes.reset();
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try std.testing.expect(nes.cpu.registers.pc != 0x1234);
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// Load state
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try nes.loadState(save_buf[0..bytes_written]);
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try std.testing.expectEqual(@as(u16, 0x1234), nes.cpu.registers.pc);
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try std.testing.expectEqual(@as(u8, 0x42), nes.cpu.registers.a);
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try std.testing.expectEqual(@as(u8, 0xAA), nes.bus.ram[0x05]);
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try std.testing.expectEqual(@as(u16, 0x2050), nes.bus.ppu.vram_addr);
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}
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comptime {
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contract.validateSystem(Nes);
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}
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