1491 lines
44 KiB
Zig
1491 lines
44 KiB
Zig
const types = @import("types.zig");
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const Model = types.Model;
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const Registers = types.Registers;
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const Instruction = @import("instruction.zig");
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const AddressingMode = Instruction.AddressingMode;
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const Alu = @import("alu.zig");
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const Addressing = @import("addressing.zig");
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const utils = @import("utils.zig");
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pub const disassembler = @import("disassembler.zig");
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pub const mos6510 = @import("mos6510.zig");
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pub const Vector = enum(u16) {
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nmi = 0xfffa,
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reset = 0xfffc,
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irq = 0xfffe,
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};
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const CpuState = enum {
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running,
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waiting,
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stopped,
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jammed,
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};
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pub const Accuracy = enum {
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instruction,
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cycle,
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};
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pub const CpuSnapshot = struct {
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registers: Registers,
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cycles: u64,
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state: CpuState,
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nmi_line: bool,
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nmi_latch: bool,
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nmi_pending: bool,
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irq_asserted: bool,
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};
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pub fn Cpu(
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comptime Bus: type,
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comptime model: Model,
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comptime accuracy: Accuracy,
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) type {
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return CpuWithHook(Bus, model, accuracy, void);
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}
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pub fn CpuWithHook(
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comptime Bus: type,
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comptime model: Model,
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comptime accuracy: Accuracy,
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comptime Hook: type,
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) type {
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comptime {
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utils.validateBus(Bus);
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if (accuracy == .cycle and !@hasDecl(Bus, "tick")) {
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@compileError(
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"Cycle-accurate CPU mode requires Bus.tick(self: *Bus) void",
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);
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}
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}
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return struct {
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pub const cpu_model = model;
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pub const cpu_accuracy = accuracy;
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pub const features = model.features();
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pub const instruction_table = model.instructionTable();
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pub const address_mask = model.addressMask();
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bus: *Bus,
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registers: Registers = .{},
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cycles: u64 = 0,
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state: CpuState = .running,
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nmi_line: bool = false,
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nmi_latch: bool = false,
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nmi_pending: bool = false,
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irq_asserted: bool = false,
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const Self = @This();
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// Public API & Lifecycle
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pub fn init(bus: *Bus) Self {
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return .{
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.bus = bus,
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};
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}
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pub fn saveState(self: *const Self) CpuSnapshot {
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return .{
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.registers = self.registers,
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.cycles = self.cycles,
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.state = self.state,
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.nmi_line = self.nmi_line,
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.nmi_latch = self.nmi_latch,
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.nmi_pending = self.nmi_pending,
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.irq_asserted = self.irq_asserted,
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};
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}
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pub fn loadState(self: *Self, snapshot: CpuSnapshot) void {
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self.registers = snapshot.registers;
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self.cycles = snapshot.cycles;
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self.state = snapshot.state;
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self.nmi_line = snapshot.nmi_line;
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self.nmi_latch = snapshot.nmi_latch;
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self.nmi_pending = snapshot.nmi_pending;
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self.irq_asserted = snapshot.irq_asserted;
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}
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pub fn setNmi(self: *Self, active: bool) void {
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if (self.nmi_line and !active) {
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self.nmi_latch = true;
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}
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self.nmi_line = active;
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}
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pub fn reset(self: *Self) void {
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self.state = .running;
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self.nmi_line = false;
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self.nmi_latch = false;
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self.nmi_pending = false;
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self.irq_asserted = false;
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self.cycles = 0;
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self.registers.status.interrupt_disable = true;
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if (features.cmos_instructions) {
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self.registers.status.decimal = false;
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}
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self.registers.sp = 0x00;
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_ = self.readCycle(self.registers.pc);
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_ = self.readCycle(self.registers.pc);
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for (0..3) |_| {
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_ = self.readCycle(
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0x0100 | @as(u16, self.registers.sp),
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);
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self.registers.sp -%= 1;
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}
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const low = self.readCycle(@intFromEnum(Vector.reset));
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const high = self.readCycle(@intFromEnum(Vector.reset) + 1);
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self.registers.pc = utils.makeWord(low, high);
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}
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pub fn step(self: *Self) ?u8 {
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if (self.state == .stopped or
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self.state == .jammed)
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{
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return null;
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}
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const start = self.cycles;
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if (self.nmi_latch or self.nmi_pending) {
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self.nmi_latch = false;
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self.nmi_pending = false;
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self.wakeFromWait();
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self.handleInterrupt(@intFromEnum(Vector.nmi));
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return @intCast(self.cycles -% start);
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}
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if (self.irq_asserted) {
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self.wakeFromWait();
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if (!self.registers.status.interrupt_disable) {
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self.handleInterrupt(@intFromEnum(Vector.irq));
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return @intCast(self.cycles -% start);
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}
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}
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if (self.state == .waiting)
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return null;
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const pc_before = self.registers.pc;
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const opcode = self.fetchByte();
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const instruction = instruction_table[opcode];
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if (Hook != void) {
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Hook.onStep(self, pc_before, opcode, instruction);
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}
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self.execute(instruction);
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return @intCast(self.cycles -% start);
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}
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fn wakeFromWait(self: *Self) void {
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if (self.state == .waiting)
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self.state = .running;
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}
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// Execution Dispatch
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fn execute(self: *Self, instruction: Instruction) void {
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switch (instruction.operation) {
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// Load & Store Instructions
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.lda => self.executeRead(instruction.mode, Self.lda),
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.ldx => self.executeRead(instruction.mode, Self.ldx),
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.ldy => self.executeRead(instruction.mode, Self.ldy),
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.sta => self.executeWrite(instruction.mode, self.registers.a),
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.stx => self.executeWrite(instruction.mode, self.registers.x),
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.sty => self.executeWrite(instruction.mode, self.registers.y),
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.stz => self.executeWrite(instruction.mode, 0),
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// Register Transfers & Stack Operations
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.tax => self.executeImplied(Self.tax),
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.txa => self.executeImplied(Self.txa),
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.tay => self.executeImplied(Self.tay),
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.tya => self.executeImplied(Self.tya),
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.tsx => self.executeImplied(Self.tsx),
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.txs => self.executeImplied(Self.txs),
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.pha => self.pha(),
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.php => self.php(),
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.pla => self.pla(),
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.plp => self.plp(),
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.phx => self.phx(),
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.phy => self.phy(),
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.plx => self.plx(),
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.ply => self.ply(),
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// Arithmetic & Logical Instructions
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.adc => self.executeRead(instruction.mode, Self.adc),
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.sbc => self.executeRead(instruction.mode, Self.sbc),
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.@"and" => self.executeRead(instruction.mode, Self.@"and"),
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.ora => self.executeRead(instruction.mode, Self.ora),
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.eor => self.executeRead(instruction.mode, Self.eor),
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.bit => self.executeBit(instruction.mode),
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.cmp => self.executeCompare(instruction.mode, self.registers.a),
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.cpx => self.executeCompare(instruction.mode, self.registers.x),
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.cpy => self.executeCompare(instruction.mode, self.registers.y),
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.trb => self.executeModify(instruction.mode, Self.trb),
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.tsb => self.executeModify(instruction.mode, Self.tsb),
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// Increments, Decrements & Shifts
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.inc => self.executeIncDec(instruction.mode, Self.inc),
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.dec => self.executeIncDec(instruction.mode, Self.dec),
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.inx => self.executeImplied(Self.inx),
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.dex => self.executeImplied(Self.dex),
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.iny => self.executeImplied(Self.iny),
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.dey => self.executeImplied(Self.dey),
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.asl => self.executeShift(instruction.mode, Self.asl),
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.lsr => self.executeShift(instruction.mode, Self.lsr),
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.rol => self.executeShift(instruction.mode, Self.rol),
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.ror => self.executeShift(instruction.mode, Self.ror),
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// Branch & Jump Instructions
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.bcc => self.branch(!self.registers.status.carry),
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.bcs => self.branch(self.registers.status.carry),
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.beq => self.branch(self.registers.status.zero),
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.bne => self.branch(!self.registers.status.zero),
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.bmi => self.branch(self.registers.status.negative),
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.bpl => self.branch(!self.registers.status.negative),
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.bvc => self.branch(!self.registers.status.overflow),
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.bvs => self.branch(self.registers.status.overflow),
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.bra => self.branch(true),
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.bbr0, .bbr1, .bbr2, .bbr3, .bbr4, .bbr5, .bbr6, .bbr7 => self.bbr(bitNumber(instruction.operation, .bbr0)),
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.bbs0, .bbs1, .bbs2, .bbs3, .bbs4, .bbs5, .bbs6, .bbs7 => self.bbs(bitNumber(instruction.operation, .bbs0)),
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.jmp => self.jmp(instruction.mode),
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.jsr => self.jsr(),
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.rti => self.rti(),
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.rts => self.rts(),
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// Flags & System Control
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.clc => self.executeImplied(Self.clc),
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.sec => self.executeImplied(Self.sec),
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.cli => self.executeImplied(Self.cli),
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.sei => self.executeImplied(Self.sei),
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.cld => self.executeImplied(Self.cld),
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.sed => self.executeImplied(Self.sed),
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.clv => self.executeImplied(Self.clv),
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.nop => self.nop(instruction.mode),
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.brk => self.brk(),
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.rmb0, .rmb1, .rmb2, .rmb3, .rmb4, .rmb5, .rmb6, .rmb7 => self.rmb(bitNumber(instruction.operation, .rmb0)),
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.smb0, .smb1, .smb2, .smb3, .smb4, .smb5, .smb6, .smb7 => self.smb(bitNumber(instruction.operation, .smb0)),
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.wai => self.wai(),
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.stp => self.stp(),
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.kil => self.kil(),
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// Undocumented NMOS 6502 Opcodes
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.ahx => self.ahx(instruction.mode),
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.alr => self.executeRead(instruction.mode, Self.alr),
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.anc => self.executeRead(instruction.mode, Self.anc),
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.arr => self.executeRead(instruction.mode, Self.arr),
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.axs => self.executeRead(instruction.mode, Self.axs),
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.dcp => self.executeModify(instruction.mode, Self.dcp),
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.isc => self.executeModify(instruction.mode, Self.isc),
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.las => self.executeRead(instruction.mode, Self.las),
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.lax => self.executeRead(instruction.mode, Self.lax),
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.rla => self.executeModify(instruction.mode, Self.rla),
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.rra => self.executeModify(instruction.mode, Self.rra),
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.sax => self.executeWrite(
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instruction.mode,
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self.registers.a & self.registers.x,
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),
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.shx => self.shx(instruction.mode),
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.shy => self.shy(instruction.mode),
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.slo => self.executeModify(instruction.mode, Self.slo),
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.sre => self.executeModify(instruction.mode, Self.sre),
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.tas => self.tas(instruction.mode),
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.xaa => self.executeRead(instruction.mode, Self.xaa),
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}
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}
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// Execution Families
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fn executeRead(
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self: *Self,
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mode: AddressingMode,
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comptime operation: fn (*Self, u8) void,
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) void {
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const value = self.readOperand(mode);
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operation(self, value);
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}
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fn executeWrite(
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self: *Self,
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mode: AddressingMode,
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value: u8,
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) void {
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self.writeOperand(mode, value);
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}
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fn executeModify(
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self: *Self,
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mode: AddressingMode,
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comptime operation: fn (*Self, u8) u8,
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) void {
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switch (mode) {
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.zero_page => {
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const address = self.fetchByte();
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self.modifyAddress(address, operation);
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},
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.zero_page_x => {
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const base = self.fetchByte();
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_ = self.readCycle(base);
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self.modifyAddress(
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base +% self.registers.x,
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operation,
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);
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},
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.absolute => {
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const address = self.fetchWord();
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self.modifyAddress(address, operation);
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},
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.absolute_x => self.modifyAbsoluteIndexed(
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self.registers.x,
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operation,
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),
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// Used by undocumented RMW instructions.
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.absolute_y => self.modifyAbsoluteIndexed(
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self.registers.y,
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operation,
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),
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.indexed_indirect_x => self.modifyIndexedIndirectX(
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operation,
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),
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.indirect_indexed_y => self.modifyIndirectIndexedY(
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operation,
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),
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else => unreachable,
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}
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}
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fn executeShift(
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self: *Self,
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mode: AddressingMode,
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comptime operation: fn (*Self, u8) u8,
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) void {
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if (mode == .accumulator) {
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self.executeAccumulator(operation);
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} else {
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self.executeModify(mode, operation);
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}
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}
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fn executeAccumulator(
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self: *Self,
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comptime operation: fn (*Self, u8) u8,
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) void {
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_ = self.readCycle(self.registers.pc);
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self.registers.a =
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operation(self, self.registers.a);
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}
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fn executeIncDec(
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self: *Self,
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mode: AddressingMode,
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comptime operation: fn (*Self, u8) u8,
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) void {
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if (mode == .accumulator) {
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self.executeAccumulator(operation);
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} else {
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self.executeModify(mode, operation);
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}
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}
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fn executeImplied(
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self: *Self,
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comptime operation: fn (*Self) void,
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) void {
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_ = self.readCycle(self.registers.pc);
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operation(self);
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}
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fn executeCompare(self: *Self, mode: AddressingMode, register: u8) void {
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const value = self.readOperand(mode);
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self.compare(register, value);
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}
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fn executeBit(self: *Self, mode: AddressingMode) void {
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const value = self.readOperand(mode);
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self.registers.status.zero =
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(self.registers.a & value) == 0;
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// 65C02 BIT #imm only affects Z.
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if (mode != .immediate) {
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self.registers.status.negative =
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(value & 0x80) != 0;
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self.registers.status.overflow =
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(value & 0x40) != 0;
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}
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}
|
|
|
|
// Bus Access & Fetch
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pub fn tick(self: *Self) void {
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self.cycles +%= 1;
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|
|
|
if (comptime @hasDecl(Bus, "tick")) {
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self.bus.tick();
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}
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}
|
|
|
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pub fn readCycle(self: *Self, address: u16) u8 {
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const value = self.bus.read(address & address_mask);
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self.tick();
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return value;
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}
|
|
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pub fn writeCycle(self: *Self, address: u16, value: u8) void {
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self.bus.write(address & address_mask, value);
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self.tick();
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}
|
|
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pub fn fetchByte(self: *Self) u8 {
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const value = self.readCycle(self.registers.pc);
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self.registers.pc +%= 1;
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return value;
|
|
}
|
|
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pub fn fetchWord(self: *Self) u16 {
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const low = self.fetchByte();
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|
const high = self.fetchByte();
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return utils.makeWord(low, high);
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|
}
|
|
|
|
// Addressing Operations
|
|
fn readOperand(self: *Self, mode: AddressingMode) u8 {
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|
return Addressing.readOperand(self, mode);
|
|
}
|
|
|
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fn writeOperand(self: *Self, mode: AddressingMode, value: u8) void {
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|
Addressing.writeOperand(self, mode, value);
|
|
}
|
|
|
|
fn modifyAddress(self: *Self, address: u16, comptime operation: fn (*Self, u8) u8) void {
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|
Addressing.modifyAddress(self, address, operation);
|
|
}
|
|
|
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fn modifyAbsoluteIndexed(self: *Self, index: u8, comptime operation: fn (*Self, u8) u8) void {
|
|
Addressing.modifyAbsoluteIndexed(self, index, operation);
|
|
}
|
|
|
|
fn modifyIndexedIndirectX(self: *Self, comptime operation: fn (*Self, u8) u8) void {
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|
Addressing.modifyIndexedIndirectX(self, operation);
|
|
}
|
|
|
|
fn modifyIndirectIndexedY(self: *Self, comptime operation: fn (*Self, u8) u8) void {
|
|
Addressing.modifyIndirectIndexedY(self, operation);
|
|
}
|
|
|
|
fn bitNumber(operation: Instruction.Operation, first: Instruction.Operation) u3 {
|
|
return Addressing.bitNumber(operation, first);
|
|
}
|
|
|
|
fn addRelative(base: u16, offset: i8) u16 {
|
|
return Addressing.addRelative(base, offset);
|
|
}
|
|
|
|
fn pageCrossed(base: u16, address: u16) bool {
|
|
return Addressing.pageCrossed(base, address);
|
|
}
|
|
|
|
fn branch(self: *Self, condition: bool) void {
|
|
const offset: i8 = @bitCast(self.fetchByte());
|
|
|
|
if (!condition)
|
|
return;
|
|
|
|
const old_pc = self.registers.pc;
|
|
const new_pc = addRelative(old_pc, offset);
|
|
|
|
_ = self.readCycle(old_pc);
|
|
|
|
if (pageCrossed(old_pc, new_pc)) {
|
|
const dummy = (old_pc & 0xff00) | (new_pc & 0x00ff);
|
|
_ = self.readCycle(dummy);
|
|
}
|
|
|
|
self.registers.pc = new_pc;
|
|
}
|
|
|
|
// Stack & Interrupt Primitives
|
|
fn push(self: *Self, value: u8) void {
|
|
self.writeCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
value,
|
|
);
|
|
|
|
self.registers.sp -%= 1;
|
|
}
|
|
|
|
fn pop(self: *Self) u8 {
|
|
self.registers.sp +%= 1;
|
|
|
|
return self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
}
|
|
|
|
fn push16(self: *Self, value: u16) void {
|
|
self.push(@truncate(value >> 8));
|
|
self.push(@truncate(value));
|
|
}
|
|
|
|
fn pop16(self: *Self) u16 {
|
|
const low = self.pop();
|
|
const high = self.pop();
|
|
return utils.makeWord(low, high);
|
|
}
|
|
|
|
fn handleInterrupt(
|
|
self: *Self,
|
|
vector: u16,
|
|
) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
self.push16(self.registers.pc);
|
|
self.push(self.registers.status.toByte(false));
|
|
|
|
self.registers.status.interrupt_disable = true;
|
|
|
|
if (features.cmos_instructions) {
|
|
self.registers.status.decimal = false;
|
|
}
|
|
|
|
const low = self.readCycle(vector);
|
|
const high = self.readCycle(vector +% 1);
|
|
|
|
self.registers.pc = utils.makeWord(low, high);
|
|
}
|
|
|
|
// Control Flow & Stack Instructions
|
|
fn brk(self: *Self) void {
|
|
// Opcode fetch already incremented PC once.
|
|
// BRK performs another read and advances PC again,
|
|
// so the stacked return address is BRK + 2.
|
|
_ = self.fetchByte();
|
|
|
|
self.push16(self.registers.pc);
|
|
|
|
// BRK pushes P with the B bit set.
|
|
self.push(self.registers.status.toByte(true));
|
|
|
|
self.registers.status.interrupt_disable = true;
|
|
|
|
// 65C02 clears decimal mode on interrupt entry.
|
|
if (features.cmos_instructions) {
|
|
self.registers.status.decimal = false;
|
|
}
|
|
|
|
const low = self.readCycle(@intFromEnum(Vector.irq));
|
|
const high = self.readCycle(@intFromEnum(Vector.irq) + 1);
|
|
|
|
self.registers.pc = utils.makeWord(low, high);
|
|
}
|
|
|
|
fn jmp(self: *Self, mode: AddressingMode) void {
|
|
switch (mode) {
|
|
.absolute => {
|
|
self.registers.pc = self.fetchWord();
|
|
},
|
|
|
|
.absolute_indexed_indirect => {
|
|
const base = self.fetchWord();
|
|
|
|
// Extra indexing cycle.
|
|
_ = self.readCycle(base);
|
|
|
|
const pointer =
|
|
base +% self.registers.x;
|
|
|
|
const low = self.readCycle(pointer);
|
|
const high = self.readCycle(pointer +% 1);
|
|
|
|
self.registers.pc =
|
|
@as(u16, low) |
|
|
(@as(u16, high) << 8);
|
|
},
|
|
|
|
.indirect => {
|
|
const pointer = self.fetchWord();
|
|
|
|
const low = self.readCycle(pointer);
|
|
|
|
const high_address =
|
|
if (features.fixed_indirect_jump)
|
|
pointer +% 1
|
|
else
|
|
(pointer & 0xff00) |
|
|
((pointer +% 1) & 0x00ff);
|
|
|
|
const high = self.readCycle(high_address);
|
|
|
|
self.registers.pc =
|
|
@as(u16, low) |
|
|
(@as(u16, high) << 8);
|
|
},
|
|
|
|
else => unreachable,
|
|
}
|
|
}
|
|
|
|
fn jsr(self: *Self) void {
|
|
const target_low = self.fetchByte();
|
|
|
|
_ = self.readCycle(0x0100 | @as(u16, self.registers.sp));
|
|
|
|
// PC currently points at the high byte of the JSR operand.
|
|
// This is the return address pushed by the 6502.
|
|
self.push16(self.registers.pc);
|
|
|
|
const target_high = self.fetchByte();
|
|
self.registers.pc = utils.makeWord(target_low, target_high);
|
|
}
|
|
|
|
fn nop(self: *Self, mode: AddressingMode) void {
|
|
switch (mode) {
|
|
.implied,
|
|
.accumulator,
|
|
=> {
|
|
_ = self.readCycle(self.registers.pc);
|
|
},
|
|
|
|
.immediate,
|
|
.zero_page,
|
|
.zero_page_x,
|
|
.zero_page_y,
|
|
.absolute,
|
|
.absolute_x,
|
|
.absolute_y,
|
|
.indirect,
|
|
.indexed_indirect_x,
|
|
.indirect_indexed_y,
|
|
.zero_page_indirect,
|
|
.absolute_indexed_indirect,
|
|
=> {
|
|
_ = self.readOperand(mode);
|
|
},
|
|
|
|
.relative => {
|
|
_ = self.fetchByte();
|
|
},
|
|
|
|
.zero_page_relative => {
|
|
_ = self.fetchByte();
|
|
_ = self.fetchByte();
|
|
},
|
|
}
|
|
}
|
|
|
|
fn pha(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
self.push(self.registers.a);
|
|
}
|
|
|
|
fn php(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
// PHP pushes status with B = 1.
|
|
self.push(self.registers.status.toByte(true));
|
|
}
|
|
|
|
fn pla(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
self.registers.a = self.pop();
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn plp(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
const value = self.pop();
|
|
self.loadStatus(value);
|
|
}
|
|
|
|
fn rti(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
self.loadStatus(self.pop());
|
|
self.registers.pc = self.pop16();
|
|
}
|
|
|
|
fn rts(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
self.registers.pc = self.pop16();
|
|
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
// JSR stores the address of its final operand byte,
|
|
// so RTS resumes at address + 1.
|
|
self.registers.pc +%= 1;
|
|
}
|
|
|
|
// Status & Comparison Helpers
|
|
fn updateNZ(self: *Self, value: u8) void {
|
|
self.registers.status.zero = value == 0;
|
|
self.registers.status.negative = value & 0x80 != 0;
|
|
}
|
|
|
|
fn loadStatus(self: *Self, value: u8) void {
|
|
self.registers.status.carry = (value & 0x01) != 0;
|
|
self.registers.status.zero = (value & 0x02) != 0;
|
|
self.registers.status.interrupt_disable = (value & 0x04) != 0;
|
|
self.registers.status.decimal = (value & 0x08) != 0;
|
|
self.registers.status.overflow = (value & 0x40) != 0;
|
|
self.registers.status.negative = (value & 0x80) != 0;
|
|
}
|
|
|
|
fn compare(self: *Self, register: u8, value: u8) void {
|
|
const result = register -% value;
|
|
self.registers.status.carry = register >= value;
|
|
self.updateNZ(result);
|
|
}
|
|
|
|
// Documented Arithmetic & Logic
|
|
fn adc(self: *Self, value: u8) void {
|
|
const accumulator = self.registers.a;
|
|
const carry: u16 = @intFromBool(self.registers.status.carry);
|
|
|
|
const sum =
|
|
@as(u16, accumulator) +
|
|
@as(u16, value) +
|
|
carry;
|
|
|
|
const binary_result: u8 = @truncate(sum);
|
|
|
|
const overflow =
|
|
((accumulator ^ binary_result) &
|
|
(value ^ binary_result) &
|
|
0x80) != 0;
|
|
|
|
const decimal =
|
|
features.decimal_arithmetic and
|
|
self.registers.status.decimal;
|
|
|
|
if (decimal and features.cmos_instructions) self.tick();
|
|
|
|
const out: struct { value: u8, carry: bool } =
|
|
if (decimal) decimal: {
|
|
const low_sum =
|
|
@as(u16, accumulator & 0x0f) +
|
|
@as(u16, value & 0x0f) +
|
|
carry;
|
|
|
|
var adjusted = sum;
|
|
|
|
if (low_sum > 9)
|
|
adjusted += 6;
|
|
|
|
const carry_out = adjusted > 0x99;
|
|
|
|
if (carry_out)
|
|
adjusted += 0x60;
|
|
|
|
break :decimal .{
|
|
.value = @truncate(adjusted),
|
|
.carry = carry_out,
|
|
};
|
|
} else .{
|
|
.value = binary_result,
|
|
.carry = sum > 0xff,
|
|
};
|
|
|
|
self.registers.status.carry = out.carry;
|
|
self.registers.status.overflow = overflow;
|
|
|
|
self.registers.a = out.value;
|
|
self.updateNZ(out.value);
|
|
}
|
|
|
|
fn @"and"(self: *Self, value: u8) void {
|
|
self.registers.a &= value;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn eor(self: *Self, value: u8) void {
|
|
self.registers.a ^= value;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn ora(self: *Self, value: u8) void {
|
|
self.registers.a |= value;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn sbc(self: *Self, value: u8) void {
|
|
const accumulator = self.registers.a;
|
|
|
|
// SBC subtracts M + (1 - C).
|
|
const borrow: u16 =
|
|
if (self.registers.status.carry) 0 else 1;
|
|
|
|
const diff: i16 =
|
|
@as(i16, accumulator) -
|
|
@as(i16, value) -
|
|
@as(i16, @intCast(borrow));
|
|
|
|
const binary_result: u8 = @truncate(@as(u16, @bitCast(diff)));
|
|
|
|
const overflow =
|
|
((accumulator ^ binary_result) &
|
|
(accumulator ^ value) &
|
|
0x80) != 0;
|
|
|
|
const no_borrow = diff >= 0;
|
|
|
|
const decimal =
|
|
features.decimal_arithmetic and
|
|
self.registers.status.decimal;
|
|
|
|
if (decimal and features.cmos_instructions) {
|
|
self.tick();
|
|
}
|
|
|
|
const result: u8 =
|
|
if (decimal) decimal: {
|
|
var low: i16 =
|
|
@as(i16, accumulator & 0x0f) -
|
|
@as(i16, value & 0x0f) -
|
|
@as(i16, @intCast(borrow));
|
|
|
|
var high: i16 =
|
|
@as(i16, accumulator >> 4) -
|
|
@as(i16, value >> 4);
|
|
|
|
if (low < 0) {
|
|
low -= 6;
|
|
high -= 1;
|
|
}
|
|
|
|
if (high < 0)
|
|
high -= 6;
|
|
|
|
break :decimal (@as(u8, @intCast(high & 0x0f)) << 4) |
|
|
@as(u8, @intCast(low & 0x0f));
|
|
} else binary_result;
|
|
|
|
self.registers.status.carry = no_borrow;
|
|
self.registers.status.overflow = overflow;
|
|
|
|
self.registers.a = result;
|
|
self.updateNZ(result);
|
|
}
|
|
|
|
// Documented Shifts & Memory Updates
|
|
fn asl(self: *Self, value: u8) u8 {
|
|
self.registers.status.carry = value & 0x80 != 0;
|
|
const result = value << 1;
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
fn lsr(self: *Self, value: u8) u8 {
|
|
self.registers.status.carry = value & 1 != 0;
|
|
const result = value >> 1;
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
fn rol(self: *Self, value: u8) u8 {
|
|
const carry: u8 =
|
|
@intFromBool(self.registers.status.carry);
|
|
|
|
self.registers.status.carry =
|
|
(value & 0x80) != 0;
|
|
|
|
const result =
|
|
(value << 1) | carry;
|
|
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
fn ror(self: *Self, value: u8) u8 {
|
|
const carry: u8 = if (self.registers.status.carry) 0x80 else 0;
|
|
self.registers.status.carry = value & 1 != 0;
|
|
const result = (value >> 1) | carry;
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
fn dec(self: *Self, value: u8) u8 {
|
|
const result = value -% 1;
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
fn inc(self: *Self, value: u8) u8 {
|
|
const result = value +% 1;
|
|
self.updateNZ(result);
|
|
return result;
|
|
}
|
|
|
|
// Documented Register Updates
|
|
fn dex(self: *Self) void {
|
|
self.registers.x -%= 1;
|
|
self.updateNZ(self.registers.x);
|
|
}
|
|
|
|
fn dey(self: *Self) void {
|
|
self.registers.y -%= 1;
|
|
self.updateNZ(self.registers.y);
|
|
}
|
|
|
|
fn inx(self: *Self) void {
|
|
self.registers.x +%= 1;
|
|
self.updateNZ(self.registers.x);
|
|
}
|
|
|
|
fn iny(self: *Self) void {
|
|
self.registers.y +%= 1;
|
|
self.updateNZ(self.registers.y);
|
|
}
|
|
|
|
fn lda(self: *Self, value: u8) void {
|
|
self.registers.a = value;
|
|
self.updateNZ(value);
|
|
}
|
|
|
|
fn ldx(self: *Self, value: u8) void {
|
|
self.registers.x = value;
|
|
self.updateNZ(value);
|
|
}
|
|
|
|
fn ldy(self: *Self, value: u8) void {
|
|
self.registers.y = value;
|
|
self.updateNZ(value);
|
|
}
|
|
|
|
fn tax(self: *Self) void {
|
|
self.registers.x = self.registers.a;
|
|
self.updateNZ(self.registers.x);
|
|
}
|
|
|
|
fn tay(self: *Self) void {
|
|
self.registers.y = self.registers.a;
|
|
self.updateNZ(self.registers.y);
|
|
}
|
|
|
|
fn tsx(self: *Self) void {
|
|
self.registers.x = self.registers.sp;
|
|
self.updateNZ(self.registers.x);
|
|
}
|
|
|
|
fn txa(self: *Self) void {
|
|
self.registers.a = self.registers.x;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn txs(self: *Self) void {
|
|
self.registers.sp = self.registers.x;
|
|
}
|
|
|
|
fn tya(self: *Self) void {
|
|
self.registers.a = self.registers.y;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
// Documented Flag Operations
|
|
fn clc(self: *Self) void {
|
|
self.registers.status.carry = false;
|
|
}
|
|
|
|
fn cld(self: *Self) void {
|
|
self.registers.status.decimal = false;
|
|
}
|
|
|
|
fn cli(self: *Self) void {
|
|
self.registers.status.interrupt_disable = false;
|
|
}
|
|
|
|
fn clv(self: *Self) void {
|
|
self.registers.status.overflow = false;
|
|
}
|
|
|
|
fn sec(self: *Self) void {
|
|
self.registers.status.carry = true;
|
|
}
|
|
|
|
fn sed(self: *Self) void {
|
|
self.registers.status.decimal = true;
|
|
}
|
|
|
|
fn sei(self: *Self) void {
|
|
self.registers.status.interrupt_disable = true;
|
|
}
|
|
|
|
// Undocumented Read/ALU Operations
|
|
fn alr(self: *Self, value: u8) void {
|
|
const result = self.registers.a & value;
|
|
|
|
self.registers.status.carry =
|
|
(result & 0x01) != 0;
|
|
|
|
self.registers.a = result >> 1;
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
fn anc(self: *Self, value: u8) void {
|
|
self.registers.a &= value;
|
|
|
|
self.updateNZ(self.registers.a);
|
|
|
|
self.registers.status.carry =
|
|
self.registers.status.negative;
|
|
}
|
|
|
|
fn arr(self: *Self, value: u8) void {
|
|
const anded = self.registers.a & value;
|
|
|
|
const carry_in: u8 =
|
|
@as(u8, @intFromBool(self.registers.status.carry)) << 7;
|
|
|
|
const result =
|
|
(anded >> 1) | carry_in;
|
|
|
|
self.registers.a = result;
|
|
self.updateNZ(result);
|
|
|
|
self.registers.status.carry =
|
|
(result & 0x40) != 0;
|
|
|
|
self.registers.status.overflow =
|
|
((result >> 6) ^ (result >> 5)) & 1 != 0;
|
|
}
|
|
|
|
fn axs(self: *Self, value: u8) void {
|
|
const source =
|
|
self.registers.a & self.registers.x;
|
|
|
|
const result = source -% value;
|
|
|
|
self.registers.status.carry =
|
|
source >= value;
|
|
|
|
self.registers.x = result;
|
|
self.updateNZ(result);
|
|
}
|
|
|
|
fn las(self: *Self, value: u8) void {
|
|
const result =
|
|
value & self.registers.sp;
|
|
|
|
self.registers.a = result;
|
|
self.registers.x = result;
|
|
self.registers.sp = result;
|
|
|
|
self.updateNZ(result);
|
|
}
|
|
|
|
fn lax(self: *Self, value: u8) void {
|
|
self.registers.a = value;
|
|
self.registers.x = value;
|
|
|
|
self.updateNZ(value);
|
|
}
|
|
|
|
fn xaa(self: *Self, value: u8) void {
|
|
self.registers.a =
|
|
self.registers.x & value;
|
|
|
|
self.updateNZ(self.registers.a);
|
|
}
|
|
|
|
// Undocumented RMW Operations
|
|
fn dcp(self: *Self, value: u8) u8 {
|
|
const result = value -% 1;
|
|
|
|
self.compare(
|
|
self.registers.a,
|
|
result,
|
|
);
|
|
|
|
return result;
|
|
}
|
|
|
|
fn isc(self: *Self, value: u8) u8 {
|
|
const result = value +% 1;
|
|
|
|
self.sbc(result);
|
|
|
|
return result;
|
|
}
|
|
|
|
fn rla(self: *Self, value: u8) u8 {
|
|
const carry_in: u8 =
|
|
@intFromBool(self.registers.status.carry);
|
|
|
|
self.registers.status.carry =
|
|
(value & 0x80) != 0;
|
|
|
|
const result =
|
|
(value << 1) | carry_in;
|
|
|
|
self.registers.a &= result;
|
|
self.updateNZ(self.registers.a);
|
|
|
|
return result;
|
|
}
|
|
|
|
fn rra(self: *Self, value: u8) u8 {
|
|
const carry_in: u8 =
|
|
@as(u8, @intFromBool(self.registers.status.carry)) << 7;
|
|
|
|
const carry_out =
|
|
(value & 0x01) != 0;
|
|
|
|
const result =
|
|
(value >> 1) | carry_in;
|
|
|
|
// ADC uses the carry generated by ROR.
|
|
self.registers.status.carry = carry_out;
|
|
|
|
self.adc(result);
|
|
|
|
return result;
|
|
}
|
|
|
|
fn slo(self: *Self, value: u8) u8 {
|
|
self.registers.status.carry =
|
|
(value & 0x80) != 0;
|
|
|
|
const result = value << 1;
|
|
|
|
self.registers.a |= result;
|
|
self.updateNZ(self.registers.a);
|
|
|
|
return result;
|
|
}
|
|
|
|
fn sre(self: *Self, value: u8) u8 {
|
|
self.registers.status.carry =
|
|
(value & 0x01) != 0;
|
|
|
|
const result = value >> 1;
|
|
|
|
self.registers.a ^= result;
|
|
self.updateNZ(self.registers.a);
|
|
|
|
return result;
|
|
}
|
|
|
|
// Undocumented Store Operations
|
|
fn ahx(self: *Self, mode: AddressingMode) void {
|
|
self.writeHighMasked(
|
|
mode,
|
|
self.registers.a & self.registers.x,
|
|
);
|
|
}
|
|
|
|
fn shx(self: *Self, mode: AddressingMode) void {
|
|
self.writeHighMasked(
|
|
mode,
|
|
self.registers.x,
|
|
);
|
|
}
|
|
|
|
fn shy(self: *Self, mode: AddressingMode) void {
|
|
self.writeHighMasked(
|
|
mode,
|
|
self.registers.y,
|
|
);
|
|
}
|
|
|
|
fn tas(self: *Self, mode: AddressingMode) void {
|
|
self.registers.sp =
|
|
self.registers.a & self.registers.x;
|
|
|
|
self.writeHighMasked(
|
|
mode,
|
|
self.registers.sp,
|
|
);
|
|
}
|
|
|
|
fn writeHighMasked(
|
|
self: *Self,
|
|
mode: AddressingMode,
|
|
source: u8,
|
|
) void {
|
|
switch (mode) {
|
|
.absolute_x => self.writeHighMaskedAbsolute(
|
|
self.registers.x,
|
|
source,
|
|
),
|
|
|
|
.absolute_y => self.writeHighMaskedAbsolute(
|
|
self.registers.y,
|
|
source,
|
|
),
|
|
|
|
.indirect_indexed_y => self.writeHighMaskedIndirectY(
|
|
source,
|
|
),
|
|
|
|
else => unreachable,
|
|
}
|
|
}
|
|
|
|
fn writeHighMaskedAbsolute(
|
|
self: *Self,
|
|
index: u8,
|
|
source: u8,
|
|
) void {
|
|
const low = self.fetchByte();
|
|
const high = self.fetchByte();
|
|
|
|
const base =
|
|
@as(u16, low) |
|
|
(@as(u16, high) << 8);
|
|
|
|
const address =
|
|
base +% index;
|
|
|
|
const dummy =
|
|
(base & 0xff00) |
|
|
(address & 0x00ff);
|
|
|
|
_ = self.readCycle(dummy);
|
|
|
|
const value =
|
|
source & (high +% 1);
|
|
|
|
const write_address =
|
|
if (pageCrossed(base, address))
|
|
(@as(u16, value) << 8) |
|
|
(address & 0x00ff)
|
|
else
|
|
address;
|
|
|
|
self.writeCycle(
|
|
write_address,
|
|
value,
|
|
);
|
|
}
|
|
|
|
fn writeHighMaskedIndirectY(
|
|
self: *Self,
|
|
source: u8,
|
|
) void {
|
|
const pointer = self.fetchByte();
|
|
|
|
const low = self.readCycle(pointer);
|
|
const high = self.readCycle(pointer +% 1);
|
|
|
|
const base =
|
|
@as(u16, low) |
|
|
(@as(u16, high) << 8);
|
|
|
|
const address =
|
|
base +% self.registers.y;
|
|
|
|
const dummy =
|
|
(base & 0xff00) |
|
|
(address & 0x00ff);
|
|
|
|
_ = self.readCycle(dummy);
|
|
|
|
const value =
|
|
source & (high +% 1);
|
|
|
|
const write_address =
|
|
if (pageCrossed(base, address))
|
|
(@as(u16, value) << 8) |
|
|
(address & 0x00ff)
|
|
else
|
|
address;
|
|
|
|
self.writeCycle(
|
|
write_address,
|
|
value,
|
|
);
|
|
}
|
|
|
|
// Jammed State
|
|
fn kil(self: *Self) void {
|
|
// Enter the jammed state after the opcode fetch.
|
|
_ = self.readCycle(self.registers.pc);
|
|
self.state = .jammed;
|
|
}
|
|
|
|
fn rmb(self: *Self, bit: u3) void {
|
|
self.modifyMemoryBit(bit, false);
|
|
}
|
|
|
|
fn smb(self: *Self, bit: u3) void {
|
|
self.modifyMemoryBit(bit, true);
|
|
}
|
|
|
|
fn bitBranch(self: *Self, bit: u3, expected_bit: bool) void {
|
|
const address = self.fetchByte();
|
|
const value = self.readCycle(address);
|
|
const offset: i8 = @bitCast(self.fetchByte());
|
|
|
|
const bit_is_set = (value & (@as(u8, 1) << bit)) != 0;
|
|
if (bit_is_set == expected_bit) {
|
|
const old_pc = self.registers.pc;
|
|
const new_pc = addRelative(old_pc, offset);
|
|
|
|
_ = self.readCycle(old_pc);
|
|
|
|
if (pageCrossed(old_pc, new_pc)) {
|
|
const dummy = (old_pc & 0xff00) | (new_pc & 0x00ff);
|
|
_ = self.readCycle(dummy);
|
|
}
|
|
|
|
self.registers.pc = new_pc;
|
|
}
|
|
}
|
|
|
|
fn bbr(self: *Self, bit: u3) void {
|
|
self.bitBranch(bit, false);
|
|
}
|
|
|
|
fn bbs(self: *Self, bit: u3) void {
|
|
self.bitBranch(bit, true);
|
|
}
|
|
|
|
fn modifyMemoryBit(
|
|
self: *Self,
|
|
bit: u3,
|
|
set: bool,
|
|
) void {
|
|
const address = self.fetchByte();
|
|
|
|
const old = self.readCycle(address);
|
|
|
|
// W65C02 RMW uses a second read rather than
|
|
// the NMOS dummy write.
|
|
_ = self.readCycle(address);
|
|
|
|
const mask: u8 =
|
|
@as(u8, 1) << bit;
|
|
|
|
const new =
|
|
if (set)
|
|
old | mask
|
|
else
|
|
old & ~mask;
|
|
|
|
self.writeCycle(address, new);
|
|
}
|
|
|
|
fn phx(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
self.push(self.registers.x);
|
|
}
|
|
|
|
fn phy(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
self.push(self.registers.y);
|
|
}
|
|
|
|
fn plx(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
self.registers.x = self.pop();
|
|
self.updateNZ(self.registers.x);
|
|
}
|
|
|
|
fn ply(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
_ = self.readCycle(
|
|
0x0100 | @as(u16, self.registers.sp),
|
|
);
|
|
|
|
self.registers.y = self.pop();
|
|
self.updateNZ(self.registers.y);
|
|
}
|
|
|
|
fn trb(self: *Self, value: u8) u8 {
|
|
self.registers.status.zero =
|
|
(self.registers.a & value) == 0;
|
|
|
|
return value & ~self.registers.a;
|
|
}
|
|
|
|
fn tsb(self: *Self, value: u8) u8 {
|
|
self.registers.status.zero =
|
|
(self.registers.a & value) == 0;
|
|
|
|
return value | self.registers.a;
|
|
}
|
|
|
|
fn wai(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
if (features.wait_and_stop) {
|
|
self.state = .waiting;
|
|
}
|
|
}
|
|
|
|
fn stp(self: *Self) void {
|
|
_ = self.readCycle(self.registers.pc);
|
|
_ = self.readCycle(self.registers.pc);
|
|
|
|
if (features.wait_and_stop) {
|
|
self.state = .stopped;
|
|
}
|
|
}
|
|
|
|
// Draft tracing helper for debugging initial execution loop
|
|
pub fn debugTraceStep(self: *Self) void {
|
|
const std = @import("std");
|
|
std.debug.print("CPU Step: PC={X:04} A={X:02} X={X:02} Y={X:02}\n", .{
|
|
self.registers.pc, self.registers.a, self.registers.x, self.registers.y,
|
|
});
|
|
}
|
|
};
|
|
}
|
|
|
|
|
|
|