148 lines
4.3 KiB
Zig
148 lines
4.3 KiB
Zig
const std = @import("std");
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const common = @import("../common.zig");
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const Mirroring = common.Mirroring;
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// ponytail: Mapper 10 (MMC4) - Fire Emblem & Fire Emblem Gaiden
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// 16KB switchable PRG at $8000, fixed last 16KB at $C000-$FFFF.
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// Dual 4KB CHR latches toggled by PPU fetches at $xFD8-$xFDF and $xFE8-$xFEF.
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pub const Mmc4 = @This();
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prg_bank: u8 = 0,
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chr_bank_0_fd: u8 = 0,
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chr_bank_0_fe: u8 = 0,
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chr_bank_1_fd: u8 = 0,
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chr_bank_1_fe: u8 = 0,
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latch_0: u1 = 0,
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latch_1: u1 = 0,
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mirroring_mode: Mirroring = .vertical,
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pub fn init() Mmc4 {
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return .{};
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}
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pub fn cpuRead(self: *const Mmc4, address: u16, prg_rom: []const u8, prg_ram: []const u8) ?u8 {
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if (address >= 0x6000 and address <= 0x7fff) {
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const offset = address - 0x6000;
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if (offset < prg_ram.len) return prg_ram[offset];
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return 0;
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}
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if (address >= 0x8000 and address <= 0xffff) {
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const total_16k_banks = @max(1, prg_rom.len / 0x4000);
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var bank: usize = 0;
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if (address < 0xc000) {
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bank = @as(usize, self.prg_bank) % total_16k_banks;
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const offset = (bank * 0x4000) + (address - 0x8000);
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if (offset < prg_rom.len) return prg_rom[offset];
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} else {
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bank = total_16k_banks - 1;
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const offset = (bank * 0x4000) + (address - 0xc000);
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if (offset < prg_rom.len) return prg_rom[offset];
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}
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return 0;
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}
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return null;
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}
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pub fn cpuWrite(self: *Mmc4, address: u16, value: u8, prg_ram: []u8) bool {
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if (address >= 0x6000 and address <= 0x7fff) {
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const offset = address - 0x6000;
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if (offset < prg_ram.len) {
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prg_ram[offset] = value;
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return true;
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}
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return false;
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}
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switch (address) {
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0xa000...0xafff => {
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self.prg_bank = value & 0x0f;
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return true;
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},
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0xb000...0xbfff => {
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self.chr_bank_0_fd = value & 0x1f;
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return true;
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},
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0xc000...0xcfff => {
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self.chr_bank_0_fe = value & 0x1f;
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return true;
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},
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0xd000...0xdfff => {
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self.chr_bank_1_fd = value & 0x1f;
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return true;
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},
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0xe000...0xefff => {
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self.chr_bank_1_fe = value & 0x1f;
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return true;
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},
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0xf000...0xffff => {
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self.mirroring_mode = if ((value & 1) == 0) .vertical else .horizontal;
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return true;
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},
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else => return false,
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}
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}
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pub fn ppuRead(self: *const Mmc4, address: u16, chr_rom: []const u8, chr_ram: []const u8, chr_is_ram: bool) ?u8 {
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if (address < 0x2000) {
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if (chr_is_ram) {
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if (address < chr_ram.len) return chr_ram[address];
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return 0;
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}
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if (chr_rom.len == 0) return 0;
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const total_4k_banks = @max(1, chr_rom.len / 0x1000);
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const bank = if (address < 0x1000)
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(if (self.latch_0 == 0) self.chr_bank_0_fd else self.chr_bank_0_fe)
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else
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(if (self.latch_1 == 0) self.chr_bank_1_fd else self.chr_bank_1_fe);
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const offset = ((@as(usize, bank) % total_4k_banks) * 0x1000) + (address & 0x0fff);
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if (offset < chr_rom.len) return chr_rom[offset];
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return 0;
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}
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return null;
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}
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pub fn ppuWrite(_: *Mmc4, address: u16, value: u8, chr_ram: []u8, chr_is_ram: bool) bool {
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if (address < 0x2000 and chr_is_ram) {
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if (address < chr_ram.len) {
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chr_ram[address] = value;
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return true;
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}
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}
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return false;
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}
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pub fn notifyPpuAddress(self: *Mmc4, address: u16) void {
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self.checkLatch(address);
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}
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inline fn checkLatch(self: *Mmc4, address: u16) void {
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switch (address) {
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0x0fd8...0x0fdf => self.latch_0 = 0,
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0x0fe8...0x0fef => self.latch_0 = 1,
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0x1fd8...0x1fdf => self.latch_1 = 0,
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0x1fe8...0x1fef => self.latch_1 = 1,
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else => {},
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}
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}
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pub fn mirroring(self: *const Mmc4) Mirroring {
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return self.mirroring_mode;
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}
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pub fn irqLine(_: *const Mmc4) bool {
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return false;
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}
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test "mmc4 latch toggling" {
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var m = Mmc4.init();
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var ram: [0x2000]u8 = undefined;
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_ = m.cpuWrite(0xa000, 3, &ram); // PRG bank 3
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try std.testing.expectEqual(@as(u8, 3), m.prg_bank);
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m.notifyPpuAddress(0x1fe8);
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try std.testing.expectEqual(@as(u1, 1), m.latch_1);
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}
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