111 lines
3.3 KiB
Zig
111 lines
3.3 KiB
Zig
const std = @import("std");
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const common = @import("../common.zig");
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const Mirroring = common.Mirroring;
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// ponytail: Mapper 34 (BNROM / NINA-001) - 32KB PRG banking, optional NINA-001 4KB CHR banking
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pub const Bnrom = @This();
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prg_bank: u8 = 0,
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chr_bank_0: u8 = 0,
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chr_bank_1: u8 = 1,
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mirroring_mode: Mirroring,
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pub fn init(initial_mirroring: Mirroring) Bnrom {
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return .{ .mirroring_mode = initial_mirroring };
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}
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pub fn cpuRead(self: *const Bnrom, address: u16, prg_rom: []const u8, prg_ram: []const u8) ?u8 {
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if (address >= 0x6000 and address <= 0x7fff) {
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const offset = address - 0x6000;
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if (offset < prg_ram.len) return prg_ram[offset];
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return 0;
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}
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if (address >= 0x8000 and address <= 0xffff) {
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const total_32k_banks = @max(1, prg_rom.len / 0x8000);
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const bank = @as(usize, self.prg_bank) % total_32k_banks;
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const offset = (bank * 0x8000) + (address - 0x8000);
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if (offset < prg_rom.len) return prg_rom[offset];
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return 0;
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}
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return null;
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}
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pub fn cpuWrite(self: *Bnrom, address: u16, value: u8, prg_ram: []u8) bool {
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if (address >= 0x6000 and address <= 0x7fff) {
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// NINA-001 registers
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switch (address) {
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0x7ffd => {
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self.prg_bank = value & 0x0f;
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return true;
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},
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0x7ffe => {
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self.chr_bank_0 = value & 0x0f;
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return true;
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},
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0x7fff => {
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self.chr_bank_1 = value & 0x0f;
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return true;
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},
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else => {
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const offset = address - 0x6000;
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if (offset < prg_ram.len) {
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prg_ram[offset] = value;
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return true;
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}
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},
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}
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}
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if (address >= 0x8000 and address <= 0xffff) {
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// BNROM: select 32KB PRG bank
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self.prg_bank = value & 0x0f;
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return true;
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}
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return false;
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}
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pub fn ppuRead(self: *const Bnrom, address: u16, chr_rom: []const u8, chr_ram: []const u8, chr_is_ram: bool) ?u8 {
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if (address < 0x2000) {
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if (chr_is_ram) {
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if (address < chr_ram.len) return chr_ram[address];
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} else if (chr_rom.len > 0) {
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const total_4k_banks = @max(1, chr_rom.len / 0x1000);
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const bank = if (address < 0x1000)
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@as(usize, self.chr_bank_0) % total_4k_banks
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else
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@as(usize, self.chr_bank_1) % total_4k_banks;
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const offset = (bank * 0x1000) + (address & 0x0fff);
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if (offset < chr_rom.len) return chr_rom[offset];
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}
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return 0;
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}
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return null;
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}
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pub fn ppuWrite(_: *Bnrom, address: u16, value: u8, chr_ram: []u8, chr_is_ram: bool) bool {
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if (address < 0x2000 and chr_is_ram) {
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if (address < chr_ram.len) {
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chr_ram[address] = value;
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return true;
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}
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}
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return false;
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}
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pub fn mirroring(self: *const Bnrom) Mirroring {
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return self.mirroring_mode;
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}
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pub fn irqLine(_: *const Bnrom) bool {
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return false;
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}
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pub fn notifyPpuAddress(_: *Bnrom, _: u16) void {}
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test "bnrom bank switching" {
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var bn = Bnrom.init(.vertical);
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var ram: [0x2000]u8 = undefined;
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_ = bn.cpuWrite(0x8000, 3, &ram);
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try std.testing.expectEqual(@as(u8, 3), bn.prg_bank);
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}
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