From 42f20478bdf1d56669b4397b6975b38d81adf8d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Burak=20=C5=9Een?= Date: Fri, 14 Aug 2026 06:48:14 +0200 Subject: [PATCH] add system contract and ricoh 2a03 cpu variant support --- src/contract/audio.zig | 33 + src/contract/common.zig | 21 + src/contract/input.zig | 156 ++++ src/contract/root.zig | 33 + src/contract/storage.zig | 30 + src/contract/system.zig | 132 ++++ src/contract/video.zig | 69 ++ src/cpu/m6502/addressing.zig | 26 +- src/cpu/m6502/alu.zig | 110 ++- src/cpu/m6502/conformance.zig | 52 +- .../conformance/6502_functional_test.bin | Bin 65536 -> 0 bytes .../65C02_extended_opcodes_test.bin | Bin 65536 -> 0 bytes src/cpu/m6502/conformance/LICENCE | 674 ------------------ src/cpu/m6502/conformance/nestest.nes | Bin 24592 -> 0 bytes src/cpu/m6502/root.zig | 515 +++++++------ src/cpu/m6502/types.zig | 9 + src/cpu/m6502/utils.zig | 13 +- src/cpu/root.zig | 20 + 18 files changed, 888 insertions(+), 1005 deletions(-) create mode 100644 src/contract/audio.zig create mode 100644 src/contract/common.zig create mode 100644 src/contract/input.zig create mode 100644 src/contract/root.zig create mode 100644 src/contract/storage.zig create mode 100644 src/contract/system.zig create mode 100644 src/contract/video.zig delete mode 100644 src/cpu/m6502/conformance/6502_functional_test.bin delete mode 100644 src/cpu/m6502/conformance/65C02_extended_opcodes_test.bin delete mode 100644 src/cpu/m6502/conformance/LICENCE delete mode 100644 src/cpu/m6502/conformance/nestest.nes diff --git a/src/contract/audio.zig b/src/contract/audio.zig new file mode 100644 index 0000000..a674cdb --- /dev/null +++ b/src/contract/audio.zig @@ -0,0 +1,33 @@ +pub const SampleFormat = enum { + u8, + i16, + i24, + i32, + f32, +}; + +/// Static description of an audio stream. +/// +/// Used for both outputs and inputs. +pub const StreamSpec = struct { + sample_rate: u32, + channels: u8, + format: SampleFormat, +}; + +/// Borrowed interleaved audio samples. +/// +/// For stereo: +/// +/// L R L R L R ... +/// +/// `frames` counts complete sample frames, not individual samples. +pub const Buffer = struct { + data: []const u8, + + frames: usize, + + sample_rate: u32, + channels: u8, + format: SampleFormat, +}; diff --git a/src/contract/common.zig b/src/contract/common.zig new file mode 100644 index 0000000..20bec76 --- /dev/null +++ b/src/contract/common.zig @@ -0,0 +1,21 @@ +const std = @import("std"); + +pub const Rational = struct { + numerator: u32, + denominator: u32 = 1, + + pub fn asF64(self: Rational) f64 { + std.debug.assert(self.denominator != 0); + + return @as(f64, @floatFromInt(self.numerator)) / + @as(f64, @floatFromInt(self.denominator)); + } +}; + +// This needs to be in individual system +// if they need it +//pub const Region = enum { +// ntsc_u, +// ntsc_j, +// pal, +//}; diff --git a/src/contract/input.zig b/src/contract/input.zig new file mode 100644 index 0000000..199eb35 --- /dev/null +++ b/src/contract/input.zig @@ -0,0 +1,156 @@ +const std = @import("std"); + +pub const AxisValue = i16; + +/// Normalized pointer coordinate. +/// +/// 0 = minimum +/// 65535 = maximum +pub const PointerState = struct { + active: bool = false, + + x: u16 = 0, + y: u16 = 0, + + pressure: u16 = 0, +}; + +pub const Vec3 = struct { + x: f32 = 0, + y: f32 = 0, + z: f32 = 0, +}; + +pub const MotionState = struct { + acceleration: Vec3 = .{}, + gyroscope: Vec3 = .{}, +}; + +/// Static capabilities of one input device/port. +pub const DeviceSpec = struct { + button_count: u8 = 0, + axis_count: u8 = 0, + pointer_count: u8 = 0, + + has_motion: bool = false, + + /// Number of independent haptic/rumble actuators. + haptic_count: u8 = 0, +}; + +/// Runtime input view supplied by a frontend. +/// +/// The frontend owns the slices. +pub const DeviceInput = struct { + buttons: u64 = 0, + + axes: []const AxisValue = &.{}, + pointers: []const PointerState = &.{}, + + motion: ?MotionState = null, + + pub fn isPressed( + self: DeviceInput, + button: usize, + ) bool { + std.debug.assert(button < 64); + + return (self.buttons & + (@as(u64, 1) << @intCast(button))) != 0; + } +}; + +/// Feedback generated by an emulated input device. +/// +/// Values are normalized: +/// +/// 0 = off +/// 65535 = maximum intensity +pub const DeviceFeedback = struct { + haptics: []const u16 = &.{}, +}; + +/// Convenience owning state for frontends/systems that want +/// compile-time fixed storage. +/// +/// This is a helper, not the actual ABI boundary. +pub fn FixedDeviceState( + comptime button_count: usize, + comptime axis_count: usize, + comptime pointer_count: usize, + comptime has_motion: bool, +) type { + comptime { + if (button_count > 64) { + @compileError( + "FixedDeviceState supports at most 64 buttons", + ); + } + } + + return struct { + buttons: u64 = 0, + + axes: [axis_count]AxisValue = + [_]AxisValue{0} ** axis_count, + + pointers: [pointer_count]PointerState = + [_]PointerState{.{}} ** pointer_count, + + motion: if (has_motion) MotionState else void = + if (has_motion) .{} else {}, + + const Self = @This(); + + pub fn isPressed( + self: *const Self, + button: usize, + ) bool { + std.debug.assert(button < button_count); + + return (self.buttons & + (@as(u64, 1) << @intCast(button))) != 0; + } + + pub fn press( + self: *Self, + button: usize, + ) void { + std.debug.assert(button < button_count); + + self.buttons |= + @as(u64, 1) << @intCast(button); + } + + pub fn release( + self: *Self, + button: usize, + ) void { + std.debug.assert(button < button_count); + + self.buttons &= + ~(@as(u64, 1) << @intCast(button)); + } + + pub fn setAxis( + self: *Self, + axis: usize, + value: AxisValue, + ) void { + std.debug.assert(axis < axis_count); + self.axes[axis] = value; + } + + pub fn view(self: *const Self) DeviceInput { + return .{ + .buttons = self.buttons, + .axes = &self.axes, + .pointers = &self.pointers, + .motion = if (has_motion) + self.motion + else + null, + }; + } + }; +} diff --git a/src/contract/root.zig b/src/contract/root.zig new file mode 100644 index 0000000..ea52102 --- /dev/null +++ b/src/contract/root.zig @@ -0,0 +1,33 @@ +pub const common = @import("common.zig"); +pub const video = @import("video.zig"); +pub const audio = @import("audio.zig"); +pub const input = @import("input.zig"); +pub const storage = @import("storage.zig"); +pub const system = @import("system.zig"); + +pub const Rational = common.Rational; + +pub const PixelFormat = video.PixelFormat; +pub const ScanMode = video.ScanMode; +pub const VideoOutputSpec = video.VideoOutputSpec; +pub const VideoFrame = video.VideoFrame; + +pub const AudioSampleFormat = audio.SampleFormat; +pub const AudioStreamSpec = audio.StreamSpec; +pub const AudioBuffer = audio.Buffer; + +pub const AxisValue = input.AxisValue; +pub const PointerState = input.PointerState; +pub const Vec3 = input.Vec3; +pub const MotionState = input.MotionState; +pub const InputDeviceSpec = input.DeviceSpec; +pub const DeviceInput = input.DeviceInput; +pub const DeviceFeedback = input.DeviceFeedback; +pub const FixedDeviceState = input.FixedDeviceState; + +pub const StorageSpec = storage.Spec; +pub const StorageView = storage.View; +pub const StorageLoadError = storage.LoadError; + +pub const SystemSpec = system.Spec; +pub const validateSystem = system.validate; diff --git a/src/contract/storage.zig b/src/contract/storage.zig new file mode 100644 index 0000000..fa0817b --- /dev/null +++ b/src/contract/storage.zig @@ -0,0 +1,30 @@ +pub const Spec = struct { + name: []const u8, + + /// Minimum accepted storage size. + min_size: usize, + + /// Maximum accepted storage size. + max_size: usize, + + persistent: bool = true, + removable: bool = false, + writable: bool = true, +}; + +/// Borrowed view of persistent system storage. +/// +/// `generation` should change whenever its contents are modified. +/// A frontend can use this to avoid unnecessarily writing unchanged +/// save data to disk. +pub const View = struct { + data: []const u8, + + generation: u64 = 0, +}; + +pub const LoadError = error{ + InvalidSlot, + InvalidSize, + ReadOnly, +}; diff --git a/src/contract/system.zig b/src/contract/system.zig new file mode 100644 index 0000000..1d18877 --- /dev/null +++ b/src/contract/system.zig @@ -0,0 +1,132 @@ +const video = @import("video.zig"); +const audio = @import("audio.zig"); +const input = @import("input.zig"); +const storage = @import("storage.zig"); + +pub const Spec = struct { + name: []const u8, + + video_outputs: []const video.VideoOutputSpec = &.{}, + + audio_outputs: []const audio.StreamSpec = &.{}, + audio_inputs: []const audio.StreamSpec = &.{}, + + input_devices: []const input.DeviceSpec = &.{}, + + storage_devices: []const storage.Spec = &.{}, +}; + +pub fn validate(comptime System: type) void { + comptime { + if (!@hasDecl(System, "spec")) { + @compileError( + "System must expose `pub const spec: contract.SystemSpec`", + ); + } + + if (@TypeOf(System.spec) != Spec) { + @compileError( + "`System.spec` must have type contract.SystemSpec", + ); + } + + requireFunction( + System, + "reset", + fn (*System) void, + ); + + requireFunction( + System, + "runFrame", + fn (*System) void, + ); + + if (System.spec.video_outputs.len != 0) { + requireFunction( + System, + "videoFrame", + fn (*const System, usize) video.VideoFrame, + ); + } + + if (System.spec.audio_outputs.len != 0) { + requireFunction( + System, + "audioBuffer", + fn (*const System, usize) audio.Buffer, + ); + } + + if (System.spec.audio_inputs.len != 0) { + requireFunction( + System, + "submitAudioInput", + fn (*System, usize, audio.Buffer) void, + ); + } + + if (System.spec.input_devices.len != 0) { + requireFunction( + System, + "setInput", + fn (*System, usize, input.DeviceInput) void, + ); + } + + var has_haptics = false; + + for (System.spec.input_devices) |device| { + if (device.haptic_count != 0) { + has_haptics = true; + break; + } + } + + if (has_haptics) { + requireFunction( + System, + "deviceFeedback", + fn (*const System, usize) input.DeviceFeedback, + ); + } + + if (System.spec.storage_devices.len != 0) { + requireFunction( + System, + "storageView", + fn (*const System, usize) storage.View, + ); + + requireFunction( + System, + "loadStorage", + fn ( + *System, + usize, + []const u8, + ) storage.LoadError!void, + ); + } + } +} + +fn requireFunction( + comptime System: type, + comptime name: []const u8, + comptime Expected: type, +) void { + if (!@hasDecl(System, name)) { + @compileError( + "System must implement `" ++ name ++ "`", + ); + } + + const Actual = @TypeOf(@field(System, name)); + + if (Actual != Expected) { + @compileError( + "`" ++ name ++ "` has an invalid signature", + ); + } +} diff --git a/src/contract/video.zig b/src/contract/video.zig new file mode 100644 index 0000000..0f5580c --- /dev/null +++ b/src/contract/video.zig @@ -0,0 +1,69 @@ +const common = @import("common.zig"); + +pub const PixelFormat = enum { + indexed8, + + rgb565, + rgb555, + rgba5551, + + rgb888, + rgba8888, + bgra8888, +}; + +pub const ScanMode = enum { + progressive, + interlaced, +}; + +pub const Field = enum { + none, + even, + odd, +}; + +/// Static capabilities of one video output. +pub const VideoOutputSpec = struct { + max_width: u16, + max_height: u16, + + /// Format exposed by this system core to the frontend. + format: PixelFormat, + + /// Nominal display aspect ratio. + aspect_ratio: common.Rational, + + /// Nominal refresh rate of this output. + refresh_rate: common.Rational, +}; + +/// One produced video frame. +/// +/// The system owns the backing memory. The frontend only borrows it. +pub const VideoFrame = struct { + data: []const u8, + + width: u16, + height: u16, + + /// Number of bytes between the beginning of consecutive rows. + pitch: usize, + + format: PixelFormat, + + scan_mode: ScanMode = .progressive, + field: Field = .none, + + /// Required when `format == .indexed8`. + /// + /// Each entry is RGBA8888. + palette: ?[]const u32 = null, + + /// Runtime display aspect ratio. + /// + /// Null means use VideoOutputSpec.aspect_ratio. + aspect_ratio: ?common.Rational = null, + + frame_number: u64 = 0, +}; diff --git a/src/cpu/m6502/addressing.zig b/src/cpu/m6502/addressing.zig index f5fcb2d..2b8435a 100644 --- a/src/cpu/m6502/addressing.zig +++ b/src/cpu/m6502/addressing.zig @@ -10,7 +10,8 @@ pub const addRelative = utils.addRelative; pub const pageCrossed = utils.pageCrossed; pub const bitNumber = utils.bitNumber; -pub fn readOperand(cpu: anytype, mode: AddressingMode) u8 { +// comptime mode parameter evaluates addressing switch at compile-time +pub inline fn readOperand(cpu: anytype, comptime mode: AddressingMode) u8 { return switch (mode) { .immediate => cpu.fetchByte(), @@ -52,7 +53,7 @@ pub fn readOperand(cpu: anytype, mode: AddressingMode) u8 { }; } -pub fn readAbsoluteIndexed(cpu: anytype, index: u8) u8 { +pub inline fn readAbsoluteIndexed(cpu: anytype, index: u8) u8 { const low = cpu.fetchByte(); const high = cpu.fetchByte(); const base = utils.makeWord(low, high); @@ -70,7 +71,7 @@ pub fn readAbsoluteIndexed(cpu: anytype, index: u8) u8 { return cpu.readCycle(address); } -pub fn readIndexedIndirectX(cpu: anytype) u8 { +pub inline fn readIndexedIndirectX(cpu: anytype) u8 { const operand = cpu.fetchByte(); _ = cpu.readCycle(operand); const pointer = operand +% cpu.registers.x; @@ -80,7 +81,7 @@ pub fn readIndexedIndirectX(cpu: anytype) u8 { return cpu.readCycle(utils.makeWord(low, high)); } -pub fn readIndirectIndexedY(cpu: anytype) u8 { +pub inline fn readIndirectIndexedY(cpu: anytype) u8 { const pointer = cpu.fetchByte(); const low = cpu.readCycle(pointer); const high = cpu.readCycle(pointer +% 1); @@ -100,7 +101,8 @@ pub fn readIndirectIndexedY(cpu: anytype) u8 { return cpu.readCycle(address); } -pub fn writeOperand(cpu: anytype, mode: AddressingMode, value: u8) void { +// comptime mode parameter evaluates addressing switch at compile-time +pub inline fn writeOperand(cpu: anytype, comptime mode: AddressingMode, value: u8) void { switch (mode) { .zero_page => { const address = cpu.fetchByte(); @@ -140,7 +142,7 @@ pub fn writeOperand(cpu: anytype, mode: AddressingMode, value: u8) void { } } -pub fn writeAbsoluteIndexed(cpu: anytype, index: u8, value: u8) void { +pub inline fn writeAbsoluteIndexed(cpu: anytype, index: u8, value: u8) void { const low = cpu.fetchByte(); const high = cpu.fetchByte(); const base = utils.makeWord(low, high); @@ -152,7 +154,7 @@ pub fn writeAbsoluteIndexed(cpu: anytype, index: u8, value: u8) void { cpu.writeCycle(address, value); } -pub fn writeIndexedIndirectX(cpu: anytype, value: u8) void { +pub inline fn writeIndexedIndirectX(cpu: anytype, value: u8) void { const operand = cpu.fetchByte(); _ = cpu.readCycle(operand); const pointer = operand +% cpu.registers.x; @@ -162,7 +164,7 @@ pub fn writeIndexedIndirectX(cpu: anytype, value: u8) void { cpu.writeCycle(utils.makeWord(low, high), value); } -pub fn writeIndirectIndexedY(cpu: anytype, value: u8) void { +pub inline fn writeIndirectIndexedY(cpu: anytype, value: u8) void { const pointer = cpu.fetchByte(); const low = cpu.readCycle(pointer); const high = cpu.readCycle(pointer +% 1); @@ -176,7 +178,7 @@ pub fn writeIndirectIndexedY(cpu: anytype, value: u8) void { cpu.writeCycle(address, value); } -pub fn modifyAddress( +pub inline fn modifyAddress( cpu: anytype, address: u16, comptime operation: fn (*@TypeOf(cpu.*), u8) u8, @@ -193,7 +195,7 @@ pub fn modifyAddress( cpu.writeCycle(address, new); } -pub fn modifyAbsoluteIndexed( +pub inline fn modifyAbsoluteIndexed( cpu: anytype, index: u8, comptime operation: fn (*@TypeOf(cpu.*), u8) u8, @@ -215,7 +217,7 @@ pub fn modifyAbsoluteIndexed( modifyAddress(cpu, address, operation); } -pub fn modifyIndexedIndirectX( +pub inline fn modifyIndexedIndirectX( cpu: anytype, comptime operation: fn (*@TypeOf(cpu.*), u8) u8, ) void { @@ -228,7 +230,7 @@ pub fn modifyIndexedIndirectX( modifyAddress(cpu, utils.makeWord(low, high), operation); } -pub fn modifyIndirectIndexedY( +pub inline fn modifyIndirectIndexedY( cpu: anytype, comptime operation: fn (*@TypeOf(cpu.*), u8) u8, ) void { diff --git a/src/cpu/m6502/alu.zig b/src/cpu/m6502/alu.zig index 784d974..f4ce4ee 100644 --- a/src/cpu/m6502/alu.zig +++ b/src/cpu/m6502/alu.zig @@ -4,15 +4,20 @@ const Instruction = @import("instruction.zig"); // pure ALU arithmetic & bitwise operations monomorphized for Cpu const Alu = @This(); +// single-pass NZ flag update via setNZ mask pub inline fn updateNZ(cpu: anytype, value: u8) void { - cpu.registers.status.zero = (value == 0); - cpu.registers.status.negative = (value & 0x80) != 0; + cpu.registers.status.setNZ(value); } +// single-pass batched status flag updates for compare, shifts, and arithmetic pub fn compare(cpu: anytype, register: u8, value: u8) void { const result = register -% value; - cpu.registers.status.carry = register >= value; - updateNZ(cpu, result); + const c: u8 = if (register >= value) 0x01 else 0; + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0x83)) | c | z | n; + cpu.registers.status = @bitCast(b); } pub fn adc(cpu: anytype, value: u8) void { @@ -27,19 +32,29 @@ pub fn adc(cpu: anytype, value: u8) void { if (decimal and cpu.model.features().cmos_instructions) cpu.tick(); - const out: struct { value: u8, carry: bool } = if (decimal) decimal: { - const low_sum = @as(u16, accumulator & 0x0f) + @as(u16, value & 0x0f) + carry; - var adjusted = sum; - if (low_sum > 9) adjusted += 6; - const carry_out = adjusted > 0x99; - if (carry_out) adjusted += 0x60; - break :decimal .{ .value = @truncate(adjusted), .carry = carry_out }; - } else .{ .value = binary_result, .carry = sum > 0xff }; + if (!decimal) { + const c: u8 = if (sum > 0xff) 0x01 else 0; + const z: u8 = if (binary_result == 0) 0x02 else 0; + const v: u8 = if (overflow) 0x40 else 0; + const n: u8 = binary_result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0xc3)) | c | z | v | n; + cpu.registers.status = @bitCast(b); + cpu.registers.a = binary_result; + return; + } - cpu.registers.status.carry = out.carry; + const low_sum = @as(u16, accumulator & 0x0f) + @as(u16, value & 0x0f) + carry; + var adjusted = sum; + if (low_sum > 9) adjusted += 6; + const carry_out = adjusted > 0x99; + if (carry_out) adjusted += 0x60; + const dec_val: u8 = @truncate(adjusted); + + cpu.registers.status.carry = carry_out; cpu.registers.status.overflow = overflow; - cpu.registers.a = out.value; - updateNZ(cpu, out.value); + cpu.registers.a = dec_val; + updateNZ(cpu, dec_val); } pub fn sbc(cpu: anytype, value: u8) void { @@ -54,49 +69,74 @@ pub fn sbc(cpu: anytype, value: u8) void { if (decimal and cpu.model.features().cmos_instructions) cpu.tick(); - const result: u8 = if (decimal) decimal: { - var low: i16 = @as(i16, accumulator & 0x0f) - @as(i16, value & 0x0f) - @as(i16, @intCast(borrow)); - var high: i16 = @as(i16, accumulator >> 4) - @as(i16, value >> 4); - if (low < 0) { - low -= 6; - high -= 1; - } - if (high < 0) high -= 6; - break :decimal (@as(u8, @intCast(high & 0x0f)) << 4) | @as(u8, @intCast(low & 0x0f)); - } else binary_result; + if (!decimal) { + const c: u8 = if (no_borrow) 0x01 else 0; + const z: u8 = if (binary_result == 0) 0x02 else 0; + const v: u8 = if (overflow) 0x40 else 0; + const n: u8 = binary_result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0xc3)) | c | z | v | n; + cpu.registers.status = @bitCast(b); + cpu.registers.a = binary_result; + return; + } + + var low: i16 = @as(i16, accumulator & 0x0f) - @as(i16, value & 0x0f) - @as(i16, @intCast(borrow)); + var high: i16 = @as(i16, accumulator >> 4) - @as(i16, value >> 4); + if (low < 0) { + low -= 6; + high -= 1; + } + if (high < 0) high -= 6; + const dec_val: u8 = (@as(u8, @intCast(high & 0x0f)) << 4) | @as(u8, @intCast(low & 0x0f)); cpu.registers.status.carry = no_borrow; cpu.registers.status.overflow = overflow; - cpu.registers.a = result; - updateNZ(cpu, result); + cpu.registers.a = dec_val; + updateNZ(cpu, dec_val); } pub fn asl(cpu: anytype, value: u8) u8 { - cpu.registers.status.carry = (value & 0x80) != 0; + const carry: u8 = (value >> 7); const result = value << 1; - updateNZ(cpu, result); + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0x83)) | carry | z | n; + cpu.registers.status = @bitCast(b); return result; } pub fn lsr(cpu: anytype, value: u8) u8 { - cpu.registers.status.carry = (value & 1) != 0; + const carry: u8 = value & 1; const result = value >> 1; - updateNZ(cpu, result); + const z: u8 = if (result == 0) 0x02 else 0; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0x83)) | carry | z; + cpu.registers.status = @bitCast(b); return result; } pub fn rol(cpu: anytype, value: u8) u8 { const carry: u8 = @intFromBool(cpu.registers.status.carry); - cpu.registers.status.carry = (value & 0x80) != 0; + const carry_out: u8 = (value >> 7); const result = (value << 1) | carry; - updateNZ(cpu, result); + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0x83)) | carry_out | z | n; + cpu.registers.status = @bitCast(b); return result; } pub fn ror(cpu: anytype, value: u8) u8 { const carry: u8 = if (cpu.registers.status.carry) 0x80 else 0; - cpu.registers.status.carry = (value & 1) != 0; + const carry_out: u8 = value & 1; const result = (value >> 1) | carry; - updateNZ(cpu, result); + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(cpu.registers.status); + b = (b & ~@as(u8, 0x83)) | carry_out | z | n; + cpu.registers.status = @bitCast(b); return result; } diff --git a/src/cpu/m6502/conformance.zig b/src/cpu/m6502/conformance.zig index 0e89999..16e0457 100644 --- a/src/cpu/m6502/conformance.zig +++ b/src/cpu/m6502/conformance.zig @@ -36,20 +36,39 @@ pub fn CycleCpu(comptime model: Model) type { return root.Cpu(TestBus, model, .cycle); } -pub const functional_test_bin = @embedFile("conformance/6502_functional_test.bin"); -pub const cmos_extended_test_bin = @embedFile("conformance/65C02_extended_opcodes_test.bin"); -pub const nestest_nes = @embedFile("conformance/nestest.nes"); +const build_options = @import("build_options"); + +fn loadFuncTestRomAlloc(allocator: std.mem.Allocator, relative_path: []const u8) ![]u8 { + const base_dir = build_options.m6502_functional_tests_dir orelse return error.TestRomsNotFetched; + var dir = try std.Io.Dir.openDirAbsolute(testing.io, base_dir, .{}); + defer dir.close(testing.io); + return dir.readFileAlloc(testing.io, relative_path, allocator, @enumFromInt(10 * 1024 * 1024)); +} + +fn loadNesTestRomAlloc(allocator: std.mem.Allocator, relative_path: []const u8) ![]u8 { + const base_dir = build_options.nes_test_roms_dir orelse return error.TestRomsNotFetched; + var dir = try std.Io.Dir.openDirAbsolute(testing.io, base_dir, .{}); + defer dir.close(testing.io); + return dir.readFileAlloc(testing.io, relative_path, allocator, @enumFromInt(10 * 1024 * 1024)); +} + +const functional_test_bin_path = "bin_files/6502_functional_test.bin"; +const cmos_extended_test_bin_path = "bin_files/65C02_extended_opcodes_test.bin"; /// Runs a binary ROM conformance test against a CPU model and memory harness. pub fn runBinaryTest( comptime model: Model, comptime accuracy: Accuracy, - rom_data: []const u8, + relative_path: []const u8, load_address: u16, start_pc: u16, success_pc: u16, max_instructions: u64, ) !void { + if (build_options.m6502_functional_tests_dir == null) return error.SkipZigTest; + const rom_data = try loadFuncTestRomAlloc(testing.allocator, relative_path); + defer testing.allocator.free(rom_data); + var bus = TestBus{}; @memcpy(bus.ram[load_address .. load_address + rom_data.len], rom_data); @@ -92,6 +111,10 @@ pub fn runNesTest( comptime accuracy: Accuracy, max_instructions: u64, ) !void { + if (build_options.nes_test_roms_dir == null) return error.SkipZigTest; + const nestest_nes = try loadNesTestRomAlloc(testing.allocator, "other/nestest.nes"); + defer testing.allocator.free(nestest_nes); + var bus = TestBus{}; // PRG ROM is 16KB starting at byte 16 (after 16-byte iNES header) const prg = nestest_nes[16 .. 16 + 16384]; @@ -128,7 +151,7 @@ test "MOS 6502 Functional Test (Instruction Accuracy)" { try runBinaryTest( .mos6502, .instruction, - functional_test_bin, + functional_test_bin_path, 0x0000, 0x0400, 0x3469, @@ -140,7 +163,7 @@ test "MOS 6502 Functional Test (Cycle Accuracy)" { try runBinaryTest( .mos6502, .cycle, - functional_test_bin, + functional_test_bin_path, 0x0000, 0x0400, 0x3469, @@ -163,7 +186,7 @@ test "MOS 6510 Functional Test (Instruction Accuracy)" { try runBinaryTest( .mos6510, .instruction, - functional_test_bin, + functional_test_bin_path, 0x0000, 0x0400, 0x3469, @@ -175,7 +198,7 @@ test "MOS 6510 Functional Test (Cycle Accuracy)" { try runBinaryTest( .mos6510, .cycle, - functional_test_bin, + functional_test_bin_path, 0x0000, 0x0400, 0x3469, @@ -205,7 +228,7 @@ test "WDC 65C02 Extended Opcodes Test (Instruction Accuracy)" { try runBinaryTest( .wdc65c02, .instruction, - cmos_extended_test_bin, + cmos_extended_test_bin_path, 0x0000, 0x0400, 0x24f1, @@ -217,7 +240,7 @@ test "WDC 65C02 Extended Opcodes Test (Cycle Accuracy)" { try runBinaryTest( .wdc65c02, .cycle, - cmos_extended_test_bin, + cmos_extended_test_bin_path, 0x0000, 0x0400, 0x24f1, @@ -230,7 +253,7 @@ test "Rockwell R65C02 Extended Opcodes Test (Instruction Accuracy)" { try runBinaryTest( .r65c02, .instruction, - cmos_extended_test_bin, + cmos_extended_test_bin_path, 0x0000, 0x0400, 0x24f1, @@ -242,7 +265,7 @@ test "Rockwell R65C02 Extended Opcodes Test (Cycle Accuracy)" { try runBinaryTest( .r65c02, .cycle, - cmos_extended_test_bin, + cmos_extended_test_bin_path, 0x0000, 0x0400, 0x24f1, @@ -250,6 +273,7 @@ test "Rockwell R65C02 Extended Opcodes Test (Cycle Accuracy)" { ); } + // Save-State & Debug Hook Tests test "Cpu Save-State Serialization (CpuSnapshot)" { var bus = TestBus{}; @@ -276,11 +300,11 @@ test "Falling-Edge NMI Latching" { // Initial high level cpu.setNmi(true); - try testing.expect(!cpu.nmi_latch); + try testing.expect(!cpu.flags.nmi_latch); // Falling edge high -> low cpu.setNmi(false); - try testing.expect(cpu.nmi_latch); + try testing.expect(cpu.flags.nmi_latch); } test "Zero-Overhead Debug Hook (CpuWithHook)" { diff --git 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If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/src/cpu/m6502/conformance/nestest.nes b/src/cpu/m6502/conformance/nestest.nes deleted file mode 100644 index fc2a88c36db9c5c2de9cca33be0e446e12007f17..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 24592 zcmeHue|%KcweOzHWCBTq0R%?*;jy5C6&xJYs1XJP5-`rPD_v}$T=9c&FbLGf6qP<_?(wPJv(V_PI7KIVSc-e+gdOv1hI z)6f0yB_wn9THm$TUVH7e*V^Zt;hOo2&vZCg-%r)Cw?mPGdgh6i0?pGaJ~(S+TBAd2 zETmtsbnOwhrZe%87!J5d>o9w^n#cLTs)B_2akrwP5k9@j=9VBGyR4H{&Az%!@C%wCu7ubFZ2=e}Ne6dA69MCggg5+B48F{yq2me3-CN!NCoX$^Ls20hSs z==~1!^YmfSf)qt*cltx2oDV}lhok`_UMF%bK_Xkto(}U^D1#pjKhvgZ*WbNLTe@&k;_?l*Imn()h}JQJf9t2S-*T)E_3m^r8RfvvgXv( z+j4qrHL_4-wpYipOUgt4NJaG<7Pwrkd1uC0M@$*+>TScqM& zEnIca(v|hgwAJCYXJ^=dwiMS~8_cz)YK}6)TEWHr7;~=@U9>5y!!@gyE!TYW=hjVC zYdi0%JcSDv&&?fSan-fCjO(lBNR&QT}j@_u*!!j zk&tB^2e6S2{jUFJ(T6@VCeVSumN9`v=kD(?k2mdap8vr)`(wY~{6SrFT_B*d&1|!0 z^9XI)ZtbJpTC83Bc#qcouJ*-VO@B{Y_rBJ80iVVzN(E;gFe?z&B^YRc}qse25Tb{l)r1)ErVhuIlAQkHb-j?L_d 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z^)9dO<<~zdUiLaj^Rw4O;5l`XaC?2suag7S%e=Z-W3Qk2bu_=8=GWEy`kG&7^XqND zx|>&j<<`&E;rx1xdYV(0^XoI!O?#cruh+nH>UMtp2A)&Lh5np+o?F-R>wA8kAE4gn z)&2hUKmQz%dmhL?7l<7Ix5@K?x~g-6y5^i0a?TA{@!a!+I7emA5&7qd+;c_#`Qrce zoFUhF@N>`ugB}?4z@P^PJuv8jK@SXiV9*1D9vJk%pa%v$FzA6n4-9%>&;x@W81%rP O2L?Sb=z;&AJn-*m;2p96 diff --git a/src/cpu/m6502/root.zig b/src/cpu/m6502/root.zig index 42d7506..dd0741b 100644 --- a/src/cpu/m6502/root.zig +++ b/src/cpu/m6502/root.zig @@ -18,11 +18,20 @@ pub const Vector = enum(u16) { irq = 0xfffe, }; -const CpuState = enum { - running, - waiting, - stopped, - jammed, +const CpuState = enum(u4) { + running = 0, + waiting = 1, + stopped = 2, + jammed = 3, +}; + +// pack interrupt bools + state into one byte for single-load hot-path check +const CpuFlags = packed struct(u8) { + nmi_line: bool = true, + nmi_latch: bool = false, + nmi_pending: bool = false, + irq_asserted: bool = false, + state: CpuState = .running, }; pub const Accuracy = enum { @@ -33,11 +42,7 @@ pub const Accuracy = enum { pub const CpuSnapshot = struct { registers: Registers, cycles: u64, - state: CpuState, - nmi_line: bool, - nmi_latch: bool, - nmi_pending: bool, - irq_asserted: bool, + flags: CpuFlags, }; pub fn Cpu( @@ -74,12 +79,8 @@ pub fn CpuWithHook( bus: *Bus, registers: Registers = .{}, cycles: u64 = 0, - state: CpuState = .running, - - nmi_line: bool = false, - nmi_latch: bool = false, - nmi_pending: bool = false, - irq_asserted: bool = false, + // single byte holds all interrupt + state flags + flags: CpuFlags = .{}, const Self = @This(); @@ -94,38 +95,29 @@ pub fn CpuWithHook( return .{ .registers = self.registers, .cycles = self.cycles, - .state = self.state, - .nmi_line = self.nmi_line, - .nmi_latch = self.nmi_latch, - .nmi_pending = self.nmi_pending, - .irq_asserted = self.irq_asserted, + .flags = self.flags, }; } pub fn loadState(self: *Self, snapshot: CpuSnapshot) void { self.registers = snapshot.registers; self.cycles = snapshot.cycles; - self.state = snapshot.state; - self.nmi_line = snapshot.nmi_line; - self.nmi_latch = snapshot.nmi_latch; - self.nmi_pending = snapshot.nmi_pending; - self.irq_asserted = snapshot.irq_asserted; + self.flags = snapshot.flags; } - pub fn setNmi(self: *Self, active: bool) void { - if (self.nmi_line and !active) { - self.nmi_latch = true; + pub inline fn setNmi(self: *Self, active: bool) void { + if (self.flags.nmi_line and !active) { + self.flags.nmi_latch = true; } - self.nmi_line = active; + self.flags.nmi_line = active; + } + + pub inline fn setIrq(self: *Self, active: bool) void { + self.flags.irq_asserted = active; } pub fn reset(self: *Self) void { - self.state = .running; - - self.nmi_line = false; - self.nmi_latch = false; - self.nmi_pending = false; - self.irq_asserted = false; + self.flags = .{}; self.cycles = 0; self.registers.status.interrupt_disable = true; @@ -152,64 +144,78 @@ pub fn CpuWithHook( self.registers.pc = utils.makeWord(low, high); } + // single byte test for interrupt/state check pub fn step(self: *Self) ?u8 { - if (self.state == .stopped or - self.state == .jammed) - { - return null; - } - const start = self.cycles; - if (self.nmi_latch or self.nmi_pending) { - self.nmi_latch = false; - self.nmi_pending = false; - self.wakeFromWait(); - self.handleInterrupt(@intFromEnum(Vector.nmi)); - return @intCast(self.cycles -% start); - } + if (@as(u8, @bitCast(self.flags)) != 0) { + if (self.flags.state == .stopped or self.flags.state == .jammed) + return null; - if (self.irq_asserted) { - self.wakeFromWait(); - - if (!self.registers.status.interrupt_disable) { - self.handleInterrupt(@intFromEnum(Vector.irq)); + if (self.flags.nmi_latch or self.flags.nmi_pending) { + self.flags.nmi_latch = false; + self.flags.nmi_pending = false; + self.wakeFromWait(); + self.handleInterrupt(@intFromEnum(Vector.nmi)); return @intCast(self.cycles -% start); } - } - if (self.state == .waiting) - return null; + if (self.flags.irq_asserted) { + self.wakeFromWait(); + + if (!self.registers.status.interrupt_disable) { + self.handleInterrupt(@intFromEnum(Vector.irq)); + return @intCast(self.cycles -% start); + } + } + + if (self.flags.state == .waiting) + return null; + } const pc_before = self.registers.pc; const opcode = self.fetchByte(); - const instruction = instruction_table[opcode]; if (Hook != void) { + const instruction = instruction_table[opcode]; Hook.onStep(self, pc_before, opcode, instruction); } - self.execute(instruction); + self.executeOpcode(opcode); return @intCast(self.cycles -% start); } fn wakeFromWait(self: *Self) void { - if (self.state == .waiting) - self.state = .running; + if (self.flags.state == .waiting) + self.flags.state = .running; } // Execution Dispatch - fn execute(self: *Self, instruction: Instruction) void { - switch (instruction.operation) { + // comptime single-stage opcode dispatch eliminates 2-stage runtime mode branching + pub fn executeOpcode(self: *Self, opcode: u8) void { + switch (opcode) { + inline 0...255 => |op| { + const inst = instruction_table[op]; + self.executeInst(inst.operation, inst.mode); + }, + } + } + + fn executeInst( + self: *Self, + comptime op: Instruction.Operation, + comptime mode: AddressingMode, + ) void { + switch (op) { // Load & Store Instructions - .lda => self.executeRead(instruction.mode, Self.lda), - .ldx => self.executeRead(instruction.mode, Self.ldx), - .ldy => self.executeRead(instruction.mode, Self.ldy), - .sta => self.executeWrite(instruction.mode, self.registers.a), - .stx => self.executeWrite(instruction.mode, self.registers.x), - .sty => self.executeWrite(instruction.mode, self.registers.y), - .stz => self.executeWrite(instruction.mode, 0), + .lda => self.executeRead(mode, Self.lda), + .ldx => self.executeRead(mode, Self.ldx), + .ldy => self.executeRead(mode, Self.ldy), + .sta => self.executeWrite(mode, self.registers.a), + .stx => self.executeWrite(mode, self.registers.x), + .sty => self.executeWrite(mode, self.registers.y), + .stz => self.executeWrite(mode, 0), // Register Transfers & Stack Operations .tax => self.executeImplied(Self.tax), @@ -228,29 +234,29 @@ pub fn CpuWithHook( .ply => self.ply(), // Arithmetic & Logical Instructions - .adc => self.executeRead(instruction.mode, Self.adc), - .sbc => self.executeRead(instruction.mode, Self.sbc), - .@"and" => self.executeRead(instruction.mode, Self.@"and"), - .ora => self.executeRead(instruction.mode, Self.ora), - .eor => self.executeRead(instruction.mode, Self.eor), - .bit => self.executeBit(instruction.mode), - .cmp => self.executeCompare(instruction.mode, self.registers.a), - .cpx => self.executeCompare(instruction.mode, self.registers.x), - .cpy => self.executeCompare(instruction.mode, self.registers.y), - .trb => self.executeModify(instruction.mode, Self.trb), - .tsb => self.executeModify(instruction.mode, Self.tsb), + .adc => self.executeRead(mode, Self.adc), + .sbc => self.executeRead(mode, Self.sbc), + .@"and" => self.executeRead(mode, Self.@"and"), + .ora => self.executeRead(mode, Self.ora), + .eor => self.executeRead(mode, Self.eor), + .bit => self.executeBit(mode), + .cmp => self.executeCompare(mode, self.registers.a), + .cpx => self.executeCompare(mode, self.registers.x), + .cpy => self.executeCompare(mode, self.registers.y), + .trb => self.executeModify(mode, Self.trb), + .tsb => self.executeModify(mode, Self.tsb), // Increments, Decrements & Shifts - .inc => self.executeIncDec(instruction.mode, Self.inc), - .dec => self.executeIncDec(instruction.mode, Self.dec), + .inc => self.executeIncDec(mode, Self.inc), + .dec => self.executeIncDec(mode, Self.dec), .inx => self.executeImplied(Self.inx), .dex => self.executeImplied(Self.dex), .iny => self.executeImplied(Self.iny), .dey => self.executeImplied(Self.dey), - .asl => self.executeShift(instruction.mode, Self.asl), - .lsr => self.executeShift(instruction.mode, Self.lsr), - .rol => self.executeShift(instruction.mode, Self.rol), - .ror => self.executeShift(instruction.mode, Self.ror), + .asl => self.executeShift(mode, Self.asl), + .lsr => self.executeShift(mode, Self.lsr), + .rol => self.executeShift(mode, Self.rol), + .ror => self.executeShift(mode, Self.ror), // Branch & Jump Instructions .bcc => self.branch(!self.registers.status.carry), @@ -262,9 +268,9 @@ pub fn CpuWithHook( .bvc => self.branch(!self.registers.status.overflow), .bvs => self.branch(self.registers.status.overflow), .bra => self.branch(true), - .bbr0, .bbr1, .bbr2, .bbr3, .bbr4, .bbr5, .bbr6, .bbr7 => self.bbr(bitNumber(instruction.operation, .bbr0)), - .bbs0, .bbs1, .bbs2, .bbs3, .bbs4, .bbs5, .bbs6, .bbs7 => self.bbs(bitNumber(instruction.operation, .bbs0)), - .jmp => self.jmp(instruction.mode), + .bbr0, .bbr1, .bbr2, .bbr3, .bbr4, .bbr5, .bbr6, .bbr7 => self.bbr(bitNumber(op, .bbr0)), + .bbs0, .bbs1, .bbs2, .bbs3, .bbs4, .bbs5, .bbs6, .bbs7 => self.bbs(bitNumber(op, .bbs0)), + .jmp => self.jmp(mode), .jsr => self.jsr(), .rti => self.rti(), .rts => self.rts(), @@ -277,43 +283,43 @@ pub fn CpuWithHook( .cld => self.executeImplied(Self.cld), .sed => self.executeImplied(Self.sed), .clv => self.executeImplied(Self.clv), - .nop => self.nop(instruction.mode), + .nop => self.nop(mode), .brk => self.brk(), - .rmb0, .rmb1, .rmb2, .rmb3, .rmb4, .rmb5, .rmb6, .rmb7 => self.rmb(bitNumber(instruction.operation, .rmb0)), - .smb0, .smb1, .smb2, .smb3, .smb4, .smb5, .smb6, .smb7 => self.smb(bitNumber(instruction.operation, .smb0)), + .rmb0, .rmb1, .rmb2, .rmb3, .rmb4, .rmb5, .rmb6, .rmb7 => self.rmb(bitNumber(op, .rmb0)), + .smb0, .smb1, .smb2, .smb3, .smb4, .smb5, .smb6, .smb7 => self.smb(bitNumber(op, .smb0)), .wai => self.wai(), .stp => self.stp(), .kil => self.kil(), // Undocumented NMOS 6502 Opcodes - .ahx => self.ahx(instruction.mode), - .alr => self.executeRead(instruction.mode, Self.alr), - .anc => self.executeRead(instruction.mode, Self.anc), - .arr => self.executeRead(instruction.mode, Self.arr), - .axs => self.executeRead(instruction.mode, Self.axs), - .dcp => self.executeModify(instruction.mode, Self.dcp), - .isc => self.executeModify(instruction.mode, Self.isc), - .las => self.executeRead(instruction.mode, Self.las), - .lax => self.executeRead(instruction.mode, Self.lax), - .rla => self.executeModify(instruction.mode, Self.rla), - .rra => self.executeModify(instruction.mode, Self.rra), + .ahx => self.ahx(mode), + .alr => self.executeRead(mode, Self.alr), + .anc => self.executeRead(mode, Self.anc), + .arr => self.executeRead(mode, Self.arr), + .axs => self.executeRead(mode, Self.axs), + .dcp => self.executeModify(mode, Self.dcp), + .isc => self.executeModify(mode, Self.isc), + .las => self.executeRead(mode, Self.las), + .lax => self.executeRead(mode, Self.lax), + .rla => self.executeModify(mode, Self.rla), + .rra => self.executeModify(mode, Self.rra), .sax => self.executeWrite( - instruction.mode, + mode, self.registers.a & self.registers.x, ), - .shx => self.shx(instruction.mode), - .shy => self.shy(instruction.mode), - .slo => self.executeModify(instruction.mode, Self.slo), - .sre => self.executeModify(instruction.mode, Self.sre), - .tas => self.tas(instruction.mode), - .xaa => self.executeRead(instruction.mode, Self.xaa), + .shx => self.shx(mode), + .shy => self.shy(mode), + .slo => self.executeModify(mode, Self.slo), + .sre => self.executeModify(mode, Self.sre), + .tas => self.tas(mode), + .xaa => self.executeRead(mode, Self.xaa), } } // Execution Families fn executeRead( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, comptime operation: fn (*Self, u8) void, ) void { const value = self.readOperand(mode); @@ -322,7 +328,7 @@ pub fn CpuWithHook( fn executeWrite( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, value: u8, ) void { self.writeOperand(mode, value); @@ -330,7 +336,7 @@ pub fn CpuWithHook( fn executeModify( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, comptime operation: fn (*Self, u8) u8, ) void { switch (mode) { @@ -380,7 +386,7 @@ pub fn CpuWithHook( fn executeShift( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, comptime operation: fn (*Self, u8) u8, ) void { if (mode == .accumulator) { @@ -402,7 +408,7 @@ pub fn CpuWithHook( fn executeIncDec( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, comptime operation: fn (*Self, u8) u8, ) void { if (mode == .accumulator) { @@ -420,12 +426,12 @@ pub fn CpuWithHook( operation(self); } - fn executeCompare(self: *Self, mode: AddressingMode, register: u8) void { + fn executeCompare(self: *Self, comptime mode: AddressingMode, register: u8) void { const value = self.readOperand(mode); self.compare(register, value); } - fn executeBit(self: *Self, mode: AddressingMode) void { + fn executeBit(self: *Self, comptime mode: AddressingMode) void { const value = self.readOperand(mode); self.registers.status.zero = @@ -441,76 +447,84 @@ pub fn CpuWithHook( } } - // Bus Access & Fetch - pub fn tick(self: *Self) void { + // bypass bus.tick() in instruction accuracy mode to eliminate unnecessary function overhead + pub inline fn tick(self: *Self) void { self.cycles +%= 1; - if (comptime @hasDecl(Bus, "tick")) { - self.bus.tick(); + if (accuracy == .cycle) { + if (comptime @hasDecl(Bus, "tick")) { + self.bus.tick(); + } + if (comptime @hasDecl(Bus, "nmiLine")) { + self.setNmi(!self.bus.nmiLine()); + } + if (comptime @hasDecl(Bus, "irqLine")) { + self.setIrq(self.bus.irqLine()); + } } } - pub fn readCycle(self: *Self, address: u16) u8 { + pub inline fn readCycle(self: *Self, address: u16) u8 { const value = self.bus.read(address & address_mask); self.tick(); return value; } - pub fn writeCycle(self: *Self, address: u16, value: u8) void { + pub inline fn writeCycle(self: *Self, address: u16, value: u8) void { self.bus.write(address & address_mask, value); self.tick(); } - pub fn fetchByte(self: *Self) u8 { + pub inline fn fetchByte(self: *Self) u8 { const value = self.readCycle(self.registers.pc); self.registers.pc +%= 1; return value; } - pub fn fetchWord(self: *Self) u16 { + pub inline fn fetchWord(self: *Self) u16 { const low = self.fetchByte(); const high = self.fetchByte(); return utils.makeWord(low, high); } // Addressing Operations - fn readOperand(self: *Self, mode: AddressingMode) u8 { + inline fn readOperand(self: *Self, comptime mode: AddressingMode) u8 { return Addressing.readOperand(self, mode); } - fn writeOperand(self: *Self, mode: AddressingMode, value: u8) void { + inline fn writeOperand(self: *Self, comptime mode: AddressingMode, value: u8) void { Addressing.writeOperand(self, mode, value); } - fn modifyAddress(self: *Self, address: u16, comptime operation: fn (*Self, u8) u8) void { + inline fn modifyAddress(self: *Self, address: u16, comptime operation: fn (*Self, u8) u8) void { Addressing.modifyAddress(self, address, operation); } - fn modifyAbsoluteIndexed(self: *Self, index: u8, comptime operation: fn (*Self, u8) u8) void { + inline fn modifyAbsoluteIndexed(self: *Self, index: u8, comptime operation: fn (*Self, u8) u8) void { Addressing.modifyAbsoluteIndexed(self, index, operation); } - fn modifyIndexedIndirectX(self: *Self, comptime operation: fn (*Self, u8) u8) void { + inline fn modifyIndexedIndirectX(self: *Self, comptime operation: fn (*Self, u8) u8) void { Addressing.modifyIndexedIndirectX(self, operation); } - fn modifyIndirectIndexedY(self: *Self, comptime operation: fn (*Self, u8) u8) void { + inline fn modifyIndirectIndexedY(self: *Self, comptime operation: fn (*Self, u8) u8) void { Addressing.modifyIndirectIndexedY(self, operation); } - fn bitNumber(operation: Instruction.Operation, first: Instruction.Operation) u3 { + inline fn bitNumber(operation: Instruction.Operation, first: Instruction.Operation) u3 { return Addressing.bitNumber(operation, first); } - fn addRelative(base: u16, offset: i8) u16 { + inline fn addRelative(base: u16, offset: i8) u16 { return Addressing.addRelative(base, offset); } - fn pageCrossed(base: u16, address: u16) bool { + inline fn pageCrossed(base: u16, address: u16) bool { return Addressing.pageCrossed(base, address); } - fn branch(self: *Self, condition: bool) void { + inline fn branch(self: *Self, condition: bool) void { const offset: i8 = @bitCast(self.fetchByte()); if (!condition) @@ -530,7 +544,7 @@ pub fn CpuWithHook( } // Stack & Interrupt Primitives - fn push(self: *Self, value: u8) void { + inline fn push(self: *Self, value: u8) void { self.writeCycle( 0x0100 | @as(u16, self.registers.sp), value, @@ -539,7 +553,7 @@ pub fn CpuWithHook( self.registers.sp -%= 1; } - fn pop(self: *Self) u8 { + inline fn pop(self: *Self) u8 { self.registers.sp +%= 1; return self.readCycle( @@ -547,12 +561,12 @@ pub fn CpuWithHook( ); } - fn push16(self: *Self, value: u16) void { + inline fn push16(self: *Self, value: u16) void { self.push(@truncate(value >> 8)); self.push(@truncate(value)); } - fn pop16(self: *Self) u16 { + inline fn pop16(self: *Self) u16 { const low = self.pop(); const high = self.pop(); return utils.makeWord(low, high); @@ -605,7 +619,7 @@ pub fn CpuWithHook( self.registers.pc = utils.makeWord(low, high); } - fn jmp(self: *Self, mode: AddressingMode) void { + fn jmp(self: *Self, comptime mode: AddressingMode) void { switch (mode) { .absolute => { self.registers.pc = self.fetchWord(); @@ -664,7 +678,7 @@ pub fn CpuWithHook( self.registers.pc = utils.makeWord(target_low, target_high); } - fn nop(self: *Self, mode: AddressingMode) void { + fn nop(self: *Self, comptime mode: AddressingMode) void { switch (mode) { .implied, .accumulator, @@ -761,25 +775,25 @@ pub fn CpuWithHook( self.registers.pc +%= 1; } - // Status & Comparison Helpers - fn updateNZ(self: *Self, value: u8) void { - self.registers.status.zero = value == 0; - self.registers.status.negative = value & 0x80 != 0; + // single-pass status helpers & ALU batched flag assignments + inline fn updateNZ(self: *Self, value: u8) void { + self.registers.status.setNZ(value); } - fn loadStatus(self: *Self, value: u8) void { - self.registers.status.carry = (value & 0x01) != 0; - self.registers.status.zero = (value & 0x02) != 0; - self.registers.status.interrupt_disable = (value & 0x04) != 0; - self.registers.status.decimal = (value & 0x08) != 0; - self.registers.status.overflow = (value & 0x40) != 0; - self.registers.status.negative = (value & 0x80) != 0; + inline fn loadStatus(self: *Self, value: u8) void { + var b = value | 0x20; + b &= ~@as(u8, 0x10); + self.registers.status = @bitCast(b); } - fn compare(self: *Self, register: u8, value: u8) void { + inline fn compare(self: *Self, register: u8, value: u8) void { const result = register -% value; - self.registers.status.carry = register >= value; - self.updateNZ(result); + const c: u8 = if (register >= value) 0x01 else 0; + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0x83)) | c | z | n; + self.registers.status = @bitCast(b); } // Documented Arithmetic & Logic @@ -787,55 +801,37 @@ pub fn CpuWithHook( const accumulator = self.registers.a; const carry: u16 = @intFromBool(self.registers.status.carry); - const sum = - @as(u16, accumulator) + - @as(u16, value) + - carry; - + const sum = @as(u16, accumulator) + @as(u16, value) + carry; const binary_result: u8 = @truncate(sum); - const overflow = - ((accumulator ^ binary_result) & - (value ^ binary_result) & - 0x80) != 0; - - const decimal = - features.decimal_arithmetic and - self.registers.status.decimal; + const overflow = ((accumulator ^ binary_result) & (value ^ binary_result) & 0x80) != 0; + const decimal = features.decimal_arithmetic and self.registers.status.decimal; if (decimal and features.cmos_instructions) self.tick(); - const out: struct { value: u8, carry: bool } = - if (decimal) decimal: { - const low_sum = - @as(u16, accumulator & 0x0f) + - @as(u16, value & 0x0f) + - carry; + if (!decimal) { + const c: u8 = if (sum > 0xff) 0x01 else 0; + const z: u8 = if (binary_result == 0) 0x02 else 0; + const v: u8 = if (overflow) 0x40 else 0; + const n: u8 = binary_result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0xc3)) | c | z | v | n; + self.registers.status = @bitCast(b); + self.registers.a = binary_result; + return; + } - var adjusted = sum; + const low_sum = @as(u16, accumulator & 0x0f) + @as(u16, value & 0x0f) + carry; + var adjusted = sum; + if (low_sum > 9) adjusted += 6; + const carry_out = adjusted > 0x99; + if (carry_out) adjusted += 0x60; + const dec_val: u8 = @truncate(adjusted); - if (low_sum > 9) - adjusted += 6; - - const carry_out = adjusted > 0x99; - - if (carry_out) - adjusted += 0x60; - - break :decimal .{ - .value = @truncate(adjusted), - .carry = carry_out, - }; - } else .{ - .value = binary_result, - .carry = sum > 0xff, - }; - - self.registers.status.carry = out.carry; + self.registers.status.carry = carry_out; self.registers.status.overflow = overflow; - - self.registers.a = out.value; - self.updateNZ(out.value); + self.registers.a = dec_val; + self.updateNZ(dec_val); } fn @"and"(self: *Self, value: u8) void { @@ -856,96 +852,93 @@ pub fn CpuWithHook( fn sbc(self: *Self, value: u8) void { const accumulator = self.registers.a; - // SBC subtracts M + (1 - C). - const borrow: u16 = - if (self.registers.status.carry) 0 else 1; - - const diff: i16 = - @as(i16, accumulator) - - @as(i16, value) - - @as(i16, @intCast(borrow)); - + const borrow: u16 = if (self.registers.status.carry) 0 else 1; + const diff: i16 = @as(i16, accumulator) - @as(i16, value) - @as(i16, @intCast(borrow)); const binary_result: u8 = @truncate(@as(u16, @bitCast(diff))); - const overflow = - ((accumulator ^ binary_result) & - (accumulator ^ value) & - 0x80) != 0; - + const overflow = ((accumulator ^ binary_result) & (accumulator ^ value) & 0x80) != 0; const no_borrow = diff >= 0; - - const decimal = - features.decimal_arithmetic and - self.registers.status.decimal; + const decimal = features.decimal_arithmetic and self.registers.status.decimal; if (decimal and features.cmos_instructions) { self.tick(); } - const result: u8 = - if (decimal) decimal: { - var low: i16 = - @as(i16, accumulator & 0x0f) - - @as(i16, value & 0x0f) - - @as(i16, @intCast(borrow)); + if (!decimal) { + const c: u8 = if (no_borrow) 0x01 else 0; + const z: u8 = if (binary_result == 0) 0x02 else 0; + const v: u8 = if (overflow) 0x40 else 0; + const n: u8 = binary_result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0xc3)) | c | z | v | n; + self.registers.status = @bitCast(b); + self.registers.a = binary_result; + return; + } - var high: i16 = - @as(i16, accumulator >> 4) - - @as(i16, value >> 4); + var low: i16 = @as(i16, accumulator & 0x0f) - @as(i16, value & 0x0f) - @as(i16, @intCast(borrow)); + var high: i16 = @as(i16, accumulator >> 4) - @as(i16, value >> 4); - if (low < 0) { - low -= 6; - high -= 1; - } + if (low < 0) { + low -= 6; + high -= 1; + } - if (high < 0) - high -= 6; + if (high < 0) + high -= 6; - break :decimal (@as(u8, @intCast(high & 0x0f)) << 4) | - @as(u8, @intCast(low & 0x0f)); - } else binary_result; + const dec_val: u8 = (@as(u8, @intCast(high & 0x0f)) << 4) | @as(u8, @intCast(low & 0x0f)); self.registers.status.carry = no_borrow; self.registers.status.overflow = overflow; - self.registers.a = result; - self.updateNZ(result); + self.registers.a = dec_val; + self.updateNZ(dec_val); } // Documented Shifts & Memory Updates fn asl(self: *Self, value: u8) u8 { - self.registers.status.carry = value & 0x80 != 0; + const carry: u8 = (value >> 7); const result = value << 1; - self.updateNZ(result); + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0x83)) | carry | z | n; + self.registers.status = @bitCast(b); return result; } fn lsr(self: *Self, value: u8) u8 { - self.registers.status.carry = value & 1 != 0; + const carry: u8 = value & 1; const result = value >> 1; - self.updateNZ(result); + const z: u8 = if (result == 0) 0x02 else 0; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0x83)) | carry | z; + self.registers.status = @bitCast(b); return result; } fn rol(self: *Self, value: u8) u8 { - const carry: u8 = - @intFromBool(self.registers.status.carry); - - self.registers.status.carry = - (value & 0x80) != 0; - - const result = - (value << 1) | carry; - - self.updateNZ(result); + const carry: u8 = @intFromBool(self.registers.status.carry); + const carry_out: u8 = (value >> 7); + const result = (value << 1) | carry; + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0x83)) | carry_out | z | n; + self.registers.status = @bitCast(b); return result; } fn ror(self: *Self, value: u8) u8 { const carry: u8 = if (self.registers.status.carry) 0x80 else 0; - self.registers.status.carry = value & 1 != 0; + const carry_out: u8 = value & 1; const result = (value >> 1) | carry; - self.updateNZ(result); + const z: u8 = if (result == 0) 0x02 else 0; + const n: u8 = result & 0x80; + var b: u8 = @bitCast(self.registers.status); + b = (b & ~@as(u8, 0x83)) | carry_out | z | n; + self.registers.status = @bitCast(b); return result; } @@ -1211,28 +1204,28 @@ pub fn CpuWithHook( } // Undocumented Store Operations - fn ahx(self: *Self, mode: AddressingMode) void { + fn ahx(self: *Self, comptime mode: AddressingMode) void { self.writeHighMasked( mode, self.registers.a & self.registers.x, ); } - fn shx(self: *Self, mode: AddressingMode) void { + fn shx(self: *Self, comptime mode: AddressingMode) void { self.writeHighMasked( mode, self.registers.x, ); } - fn shy(self: *Self, mode: AddressingMode) void { + fn shy(self: *Self, comptime mode: AddressingMode) void { self.writeHighMasked( mode, self.registers.y, ); } - fn tas(self: *Self, mode: AddressingMode) void { + fn tas(self: *Self, comptime mode: AddressingMode) void { self.registers.sp = self.registers.a & self.registers.x; @@ -1244,7 +1237,7 @@ pub fn CpuWithHook( fn writeHighMasked( self: *Self, - mode: AddressingMode, + comptime mode: AddressingMode, source: u8, ) void { switch (mode) { @@ -1345,7 +1338,7 @@ pub fn CpuWithHook( fn kil(self: *Self) void { // Enter the jammed state after the opcode fetch. _ = self.readCycle(self.registers.pc); - self.state = .jammed; + self.flags.state = .jammed; } fn rmb(self: *Self, bit: u3) void { @@ -1463,7 +1456,7 @@ pub fn CpuWithHook( _ = self.readCycle(self.registers.pc); if (features.wait_and_stop) { - self.state = .waiting; + self.flags.state = .waiting; } } @@ -1472,12 +1465,8 @@ pub fn CpuWithHook( _ = self.readCycle(self.registers.pc); if (features.wait_and_stop) { - self.state = .stopped; + self.flags.state = .stopped; } } }; } - - - - diff --git a/src/cpu/m6502/types.zig b/src/cpu/m6502/types.zig index e71cb24..3b4141c 100644 --- a/src/cpu/m6502/types.zig +++ b/src/cpu/m6502/types.zig @@ -24,6 +24,15 @@ pub const Status = packed struct(u8) { status.unused = true; return status; } + + // single-pass NZ status update via direct bitwise mask to eliminate double bitfield read-modify-write bit shifts + pub inline fn setNZ(self: *Status, value: u8) void { + const z: u8 = if (value == 0) 0x02 else 0; + const n: u8 = value & 0x80; + var b: u8 = @bitCast(self.*); + b = (b & ~@as(u8, 0x82)) | z | n; + self.* = @bitCast(b); + } }; pub const Registers = struct { diff --git a/src/cpu/m6502/utils.zig b/src/cpu/m6502/utils.zig index 1d869d0..3f59018 100644 --- a/src/cpu/m6502/utils.zig +++ b/src/cpu/m6502/utils.zig @@ -5,17 +5,16 @@ pub inline fn makeWord(low: u8, high: u8) u16 { return @as(u16, low) | (@as(u16, high) << 8); } -pub fn addRelative(base: u16, offset: i8) u16 { - const signed_offset: i16 = offset; - const unsigned_offset: u16 = @bitCast(signed_offset); - return base +% unsigned_offset; +// inline helper functions for zero call overhead +pub inline fn addRelative(base: u16, offset: i8) u16 { + return base +% @as(u16, @bitCast(@as(i16, offset))); } -pub fn pageCrossed(base: u16, address: u16) bool { - return (base & 0xff00) != (address & 0xff00); +pub inline fn pageCrossed(base: u16, address: u16) bool { + return (base ^ address) >= 0x0100; } -pub fn bitNumber(operation: anytype, first: anytype) u3 { +pub inline fn bitNumber(operation: anytype, first: anytype) u3 { return @intCast(@intFromEnum(operation) - @intFromEnum(first)); } diff --git a/src/cpu/root.zig b/src/cpu/root.zig index b632510..a4210fe 100644 --- a/src/cpu/root.zig +++ b/src/cpu/root.zig @@ -5,3 +5,23 @@ test { _ = @import("m6502/disassembler.zig"); _ = @import("m6502/mos6510.zig"); } + +const Bus = struct { + memory: [65536]u8 = [_]u8{0} ** 65536, + + pub fn read(self: *@This(), address: u16) u8 { + return self.memory[address]; + } + + pub fn write(self: *@This(), address: u16, value: u8) void { + self.memory[address] = value; + } + + pub fn tick(_: *@This()) void {} +}; + +const Cpu = m6502.Cpu(Bus, .mos6502, .cycle); + +export fn cpu_run(cpu: *Cpu) void { + _ = cpu.step(); +}